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參數(shù)資料
| 型號(hào)： | AD1866RZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC AUDIO 16BIT DUAL 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 70mW |
| 工作溫度： | -35°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，雙極 |
| 采樣率（每秒）： | * |
AD1866–Digital Circuit Considerations
REV. 0
–8–
L
S
B
M
S
B
M
S
B
L
S
B
CLK
DL
DR
LL
LR
Figure 9. AD1866 Control Signals
INPUT DATA
The digital input port of the AD1866 employs five signals: Data
Left (DL), Data Right (DR), Latch Left (LL), Latch Right
(LR), and Clock (CLK). DL and DR are the serial inputs for
the left and right DACs, respectively. Input data bits are clocked
into the input register on the rising edge of CLK. The falling
edges of LL and LR cause the last 16 bits which were clocked
into the serial registers to be shifted into the DACs, thereby up-
dating the respective DAC outputs. For systems using only a
single latch signal, LL and LR may be connected together. For
systems using only one DATA signal, DR and DL may be con-
nected together. Data is transmitted to the AD1866 in a bit
stream composed of 16-bit words with a serial, twos comple-
ment, MSB first format. Left and right channels share the Clock
(CLK) signal.
Figure 9 illustrates the general signal requirements for data
transfer for the AD1866.
TIMING
Figure 10 illustrates the specific timing requirements that must
be met in order for the data transfer to be accomplished prop-
erly. The input pins of the AD1866 are both TTL and +5 V
CMOS compatible.
>30ns
>10ns
>30ns
>15ns
>40ns
DR/DL
CLK
LR/LL
>67ns
>40ns
Figure 10. AD1866 Input Signal Timing
The maximum clock rate of the AD1866 is specified to be at
least 13.5 MHz. This clock rate allows data transfer rates of 2
×,
4
×, 8×, and 16× F
S (where FS equals 44.1 kHz). The applica-
tions section of this data sheet contains additional guidelines for
using the AD1866.
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| AD1866RZ-REEL | 功能描述:IC DAC AUDIO DUAL SGL 16SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD1868 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single Supply Dual 18-Bit Audio DAC |
| AD1868N | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 18-bit 16-Pin PDIP Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 18-BIT AUDIO DAC - Bulk 制造商:Analog Devices 功能描述:18BIT DAC DUAL AUDIO 1868 DIP16 |
| AD1868N-J | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 18-bit 16-Pin PDIP Tube 制造商:Analog Devices 功能描述:DAC 2CH R-2R 18BIT 16PDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:IC, MONO 18-BIT AUDIO DAC - Bulk |
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