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參數(shù)資料
| 型號： | AD1839AASZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 674K |
| 代理商： | AD1839AASZ1 |
AD1839A
ADC Control Registers
The AD1839A register map has five registers that are used to
control the functionality and read the status of the ADCs. The
function of the bits in each of these registers is discussed below.
ADC Peak Level
These two registers store the peak ADC result from each
channel when the ADC peak readback function is enabled. The
peak result is stored as a 6-bit number from 0 dB to 63 dB in
1 dB steps. The value contained in the register is reset once it
has been read, allowing for continuous level adjustment as
required. Note that the ADC peak level registers use the six
most significant bits in the register to store the results.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control 3 should be
programmed appropriately, based on the master clock
frequency.
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a manner similar to the DAC power-down.
Table 10. Control Register Map
Register Address
Register Name
0000
DACCTRL1
0001
DACCTRL2
0010
DACVOL1
0011
DACVOL2
0100
DACVOL3
0101
DACVOL4
0110
DACVOL5
0111
DACVOL6
1000
DACVOL7
1001
DACVOL8
1010
ADCPeak0
1011
ADCPeak1
1100
ADCCTRL1
1101
ADCCTRL2
1110
ADCCTRL3
1111
Reserved
Rev. B | Page 20 of 24
High-Pass Filter
The ADC signal path has a digital high-pass filter. Enabling this
filter removes the effect of any dc offset in the analog input
signal from the digital output codes.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Data Format
The AD1839A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I
2
S, LJ, RJ, or DSP modes.
Master/Slave Auxiliary Mode
When the AD1839A is operating in the auxiliary mode, the
auxiliary ADC control pins, AUXBCLK and AUXLRCLK, which
connect to the external ADCs, can be set to operate as a master
or slave. If the pins are set in slave mode, one of the external
ADCs should provide the LRCLK and BCLK signals.
ADC Peak Readback
Setting this bit enables ADC peak reading. See the ADCs
section for more information.
Description
DAC Control 1
DAC Control 2
DAC Volume—Left 1
DAC Volume—Right 1
DAC Volume—Left 2
DAC Volume—Right 2
DAC Volume—Left 3
DAC Volume—Right 3
DAC Volume—Left 4
DAC Volume—Right 4
ADC Left Peak
ADC Right Peak
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Width
10
10
10
10
10
10
10
10
10
10
6
6
10
10
10
10
Reset Setting (Hex)
000
000
3FF
3FF
3FF
3FF
3FF
3FF
3FF
3FF
000
000
000
000
000
Reserved
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