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參數(shù)資料
| 型號： | AD1839AASZ1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 674K |
| 代理商： | AD1839AASZ1 |
AD1839A
TABLE OF CONTENTS
Specifications.....................................................................................3
Rev. B | Page 2 of 24
Test Conditions.............................................................................3
Timing Specifications.......................................................................5
Absolute Maximum Ratings............................................................7
Temperature Range......................................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9
Terminology....................................................................................11
Functional Overview......................................................................12
ADCs............................................................................................12
DACs............................................................................................12
DAC and ADC Coding.............................................................. 12
AD1839A Clocking Scheme..................................................... 12
RESET and Power-Down.......................................................... 13
Power Supply and Voltage Reference....................................... 13
Serial Control Port..................................................................... 13
Serial Data Ports—Data Format............................................... 14
Packed Modes............................................................................. 14
Auxiliary Time Division Multiplexing (TDM) Mode........... 14
Control/Status Registers............................................................ 19
Cascade Mode............................................................................. 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format Universal
Changes to Data Sheet Title1
2/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Ordering Guide............................................................. 6
Deleted Clock Signals Section .......................................................11
Added AD1835A Clocking Scheme Section................................11
Added Table II and Table III and renumbered following tables11
Changes to Auxiliary (TDM Mode) Section................................13
Changes to Figure 5.........................................................................14
Changes to Figure 6.........................................................................14
Added Figures 7a and 8a.................................................................15
Renamed Figure 7 and Figure 8 to Figure 7b and Figure 8b .....15
Changes to Figure 9.........................................................................15
Changes to Table VIII .....................................................................21
Updated Outline Dimensions........................................................24
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