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參數(shù)資料
| 型號： | AD1839AASZ-REEL1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96 kHz, 24-Bit Sigma-Delta Codec |
| 中文描述： | 2的ADC，6 DAC的，96千赫，24位Σ-Δ編解碼器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大小： | 674K |
| 代理商： | AD1839AASZ-REEL1 |
AD1839A
Rev. B | Page 18 of 24
FSTDM
INTERNAL
ADC L1
32
AUX_ADC
L2
AUX_ADC
L3
AUX_ADC
L4
INTERNAL
ADC R1
AUX_ADC
R2
AUX_ADC
R3
AUX_ADC
R4
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
LEFT
RIGHT
I
2
S - MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX
LRCLK I
2
S
(FROM AUX ADC NO. 1)
AUX
BCLK I
2
S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
AAUXDATA3 (IN)
(FROM AUX ADC NO. 3)
AUXBCLK FREQUENCY IS 64 × FRAME RATE; TDM BCLK FREQUENCY IS 256× FRAME RATE.
T
A
2
S
MSB TDM
1ST
CH
MSB TDM
8TH
CH
I
2
S - MSB LEFT
I
2
S - MSB LEFT
I
2
S - MSB RIGHT
I
2
S - MSB RIGHT
I
2
S - MSB RIGHT
INTERNAL
DAC L4
INTERNAL
DAC R4
MSB TDM
MSB TDM
1ST
CH
8TH
CH
0
32
Figure 25. Auxiliary Mode Timing
30MHz
12.288MHz
SHARC IS ALWAYS
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
F
R
R
T
T
T
ASDATA
FSTDM
BCLK
DSDATA1
SHARC
AD1839A
MASTER
MCLK
DSDATA3/AAUXDATA2
AAUXDATA3
DSDATA2/AAUXDATA1
DLRCLK/AUXLRCLK
DBCLK/AUXBCLK
LRCLK
BCLK
DATA
MCLK
DAC NO. 1
SLAVE
DAUXDATA
0
LRCLK
BCLK
DATA
MCLK
ADC NO. 3
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC NO. 2
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC NO. 1
SLAVE
Figure 26. Auxiliary Mode Connection (Master Mode) to SHARC
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