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參數(shù)資料
| 型號(hào)： | AD1833ACSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC AUDIO 24BIT 6CH 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 12 電壓，單極 |
| 采樣率（每秒）： | 96k |
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REV. 0
AD1833A
–14–
I
2S Timing
I
2S timing uses an
L/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The
L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64
fS is used to clock in the data.
There is a delay of 1 bit clock from the time the
L/RCLK signal
changes state to the first bit of data on the SDINx lines. The data
is written MSB first and is valid on the rising edge of the bit clock.
Left-Justified Timing
Left-justified (LJ) timing uses an L/
RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
RCLK is high for the left channel and
low for the right channel. A bit clock running at 64
fS is used
LEFT CHANNEL
RIGHT CHANNEL
LSB
+1
LSB
MSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LSB
+2
MSB
–2
MSB
–1
MSB
LSB
+1
LSB
+2
MSB
–2
MSB
–1
MSB
Figure 6. I 2S Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
LSB
+1
LSB
L/RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LSB
+2
MSB
–2
MSB
–1
MSB
LSB
+1
LSB
+2
MSB
–2
MSB
–1
MSB
–1
MSB
Figure 7. Left-Justified Timing Diagram
LEFT CHANNEL
RIGHT CHANNEL
LSB
+1
LSB
L/
RCLK
INPUT
BCLK
INPUT
SDATA
INPUT
LSB
+2
MSB
–2
MSB
–1
LSB
MSB
LSB
+1
LSB
+2
MSB
–2
MSB
–1
MSB
Figure 8. Right-Justified Timing Diagram
to clock in the data. The first bit of data appears on the SDINx
lines when the L/
RCLK toggles. The data is written MSB first
and is valid on the rising edge of the bit clock.
Right-Justified Timing
Right-justified (RJ) timing uses an L/
RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/
RCLK is high for the left channel and
low for the right channel. A bit clock running at 64
fS is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/
RCLK toggles. In RJ
mode, the LSB of data is always clocked by the last bit clock
before L/
RCLK transitions. The data is written MSB first and is
valid on the rising edge of the bit clock.
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