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參數(shù)資料
| 型號： | AD1833ACSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC AUDIO 24BIT 6CH 48LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，I²S，串行 |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 12 電壓，單極 |
| 采樣率（每秒）： | 96k |
REV. 0
AD1833A
–13–
MCLK Select
The AD1833A allows the matching of available external MCLK
frequencies to the required internal MCLK rate. The MCLK
modification factor can be selected from 2, 1, or
2/
3 by writing to
Bit 4 and Bit 3 of Control Register 3. Internally, the AD1833A
requires an MCLK of 24.576 MHz for sample rates of 48 kHz,
96 kHz, and 192 kHz. In the case of 48 kHz data with an
MCLK of 256
fS, a clock doubler is used, whereas with an
MCLK of 768
fS, a divide-by-3 block ( 3) is first implemented
followed by a clock doubler. With an MCLK of 512
fS, the
MCLK is passed through unmodified (see Table XII).
Table XII. MCLK Settings
Bit 4
Bit 3
Modification Factor
00
MCLK
2 Internally
01
MCLK
1 Internally
10
MCLK
2/
3 Internally
11
Reserved
Channel Zero Status
The AD1833A provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods in all modes except right-justified. There is also
Table XIV. MCLK vs. Sample Rate Selection
Sampling Rate
Interpolator Mode
Internal MCLK
Suitable External MCLK Frequencies (MHz)
fS (kHz)
Required
Required (MHz)
MCLK
2
MCLK
1
MCLK
2/
3
32
8
64
4
16.384
8192
16.384
24.576
128
2
44.1
8
88.2
4
22.5792
11.2896
22.5792
33.8688
176.4
2
48
8
96
4
24.576
12.288
24.576
36.864
192
2
Table XV. Volume Control Registers
Address
Reserved
*
Volume Control
15–12
11
10
9–0
00
10
00
Channel 1 Volume Control (OUTL1)
00
11
Channel 2 Volume Control (OUTR1)
01
00
Channel 3 Volume Control (OUTL2)
01
Channel 4 Volume Control (OUTR2)
01
10
Channel 5 Volume Control (OUTL3)
01
11
Channel 6 Volume Control (OUTR3)
*Must be programmed to zero.
a global zero flag that indicates all channels contain zero data.
The polarity of the zero signal is programmable by writing to
Control Bit 2 (see Table XIII). In right-justified mode, the six
individual channel flags are best used as three stereo zero flags
by combining pairs of them through suitable logic gates. Then,
when both the left and right inputs are zero for 1024 clock cycles,
i.e., a stereo zero input for 1024 sample periods, the combined
result of the two individual flags will become active, indicat-
ing a stereo zero.
Table XIII. Zero Detect
Bit 2
Channel Zero Status
0Active High
1Active Low
DAC Volume Control Registers
The AD1833A has six volume control registers, one for each of
the six DAC channels. Volume control is exercised by writing to
the relevant register associated with each DAC. This setting is
used to attenuate the DAC output. Full-scale setting (all 1s) is
equivalent to zero attenuation (see Table XV).
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1833AST | 制造商:Rochester Electronics LLC 功能描述:6 CHANNEL 24 BIT 192 KHZ DAC - Tape and Reel |
| AD1833AST-REEL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1833CST-REEL | 制造商:Analog Devices 功能描述:DAC 6-CH Delta-Sigma 24-bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD1835 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
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