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參數(shù)資料
| 型號(hào)： | AD13280AZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 68CLCC |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 4.3W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-CLCC |
| 供應(yīng)商設(shè)備封裝： | 68-CLCC（24.13x24.13） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，雙極 |
| 配用： | AD13280/PCB-ND - KIT EVAL PCB FOR AD13280 |
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AD13280
Rev. C | Page 17 of 28
EVALUATION BOARD
The AD13280 evaluation board (see Figure 20) is designed to
provide optimal performance for evaluation of the AD13280
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD13280. The board requires an analog input signal, encode
clock, and power supply inputs. The clock is buffered on-board
to provide clocks for the latches. The digital outputs and out
clocks are available at the standard 40-pin connectors J1 and J2.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the associated components and the
analog section of the AD13280. The digital outputs of the
AD13280 are powered via banana jacks with 3.3 V. Contact the
factory if additional layout or applications assistance is required.
LAYOUT INFORMATION
The schematics of the evaluation board (Figure 21, Figure 22,
and Figure 23) represent a typical implementation of the
AD13280. The pinout of the AD13280 is very straightforward
and facilitates ease of use and the implementation of high
frequency/high resolution design practices. It is recommended
that high quality ceramic chip capacitors be used to decouple
each supply pin to ground directly at the device. All capacitors
can be standard, high quality ceramic chip capacitors.
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
should connect directly to the receiving gate. Internal circuitry
buffers the outputs of the ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
02
38
6-
0
20
Figure 20. Evaluation Board Mechanical Layout
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| AD-132MC | 制造商:DATEL 功能描述: |
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