參數(shù)資料
型號(hào)： ACE9030
廠商： Mitel Networks Corporation
英文描述： Radio Interface and Twin Synthesiser(用于蜂窩式電話的無(wú)線電接口電路和雙合成器)
中文描述： 無(wú)線接口和雙合成器（用于蜂窩式電話的無(wú)線電接口電路和雙合成器）
文件頁(yè)數(shù)： 31/39頁(yè)
文件大?。?/td> 379K
代理商： ACE9030
ACE9030
31
Increment
( = NF )
Accumulator
value
...previous values
5
0
3
6
1
4
7
2
5
0
and so on...
Division
Ratio
3
3
3
3
3
3
3
3
3
3
N
TOT
N
TOT
+ 1
N
TOT
N
TOT
N
TOT
+ 1
N
TOT
N
TOT
N
TOT
+ 1
N
TOT
N
TOT
+ 1
& overflows
& overflows
& overflows
& overflows
and in this case the phase error increases in the opposite
direction each cycle by:
This phase error gives an unwanted correction pulse on
the
output, as the VCO frequency is too low for the division
ratio in use.
Any phase can be considered to be the locked condition
so to simplify later calculations the phase given by a
÷
(NTOT
+ 1) cycle which leaves 000 in the accumulator will be chosen
as the locked state and compensation will be added to achieve
this. Only unwanted
outputs then need to be removed
by cancellation and also that the total phase error in any cycle,
based on formula (2), is given by replacing F, the fraction
required, by the current sum of fractions, which is the value of
the accumulator ACC divided by the modulus in use. This
replacement is clearly valid if the state of the accumulator is
considered when starting from a zero value and then adding
the fractional count each cycle until an overflow is reached;
when starting from a non-zero value there is some residual
phase error from the overflow state so the accumulator still
gives the correct phase error. Thus the phase error needing
correction on the loop filter is:
This error could be cancelled by a phase shift on the
comparison clock from the reference divider but this is very
difficult in practice so the method used in ACE9030 is to add
an extra charge pump to the loop filter to directly cancel the
pulse given by the normal charge pump due to this phase
error. The current given by the proportional charge pump is
Iprop(0) in normal mode or Iprop(1) in speed-up mode so
taking normal mode first the charge that must be cancelled is:
This formula could be used as it stands but the circuit can
be simplified if it is recalled that Iprop(0) depends on the CN
value so that loop dynamics are kept constant over a wide
range of frequencies by changing CN in proportion to the total
division ratio N
. In those systems where CN is held constant
the synthesiser is in effect considered to be operating over a
narrow frequency band so N
can also be considered
constant and the following calculations still apply. The value of
Iprop(0) is set by a DAC in ACE9030 from the reference
current Ibo so that:
and the value of CN tracks N
TOT
with a scaling factor SF such
that:
CN = SF x N
TOT
putting both of these equations into formula (5) gives the
charge to be cancelled as:
NF is the fraction set in Word A or A2
MOD is the modulus, 5 or 8
disturbed by the variations in division ratio but there is still
some frequency modulation given by the Fractional-N opera-
tion. The simplest way to remove this ripple on the synthesiser
is to use a lower bandwidth loop filter but this also removes all
of the advantage of fast channel change when using Frac-
tional-N, so the method used in ACE9030 is to calculate the
waveform of the ripple and then inject a compensation signal
onto the loop filter.
Fractional-N Compensation
If the Fractional-N system is operating correctly the
synthesiser sets the VCO frequency so that:
where F is the fraction given by:
The total division alternates between N
and N
+ 1 so
the frequency seen at the phase comparator will also alter-
nate. This divided signal f
FRACN
is compared with the uniform
comparison frequency f
the different periods. There will also be some phase error due
to leakage on the loop filter, leading to some correction pulses
on the charge pumps to maintain lock, but these will be very
small in a well designed synthesiser once the loop is locked,
so can be ignored here. For each
÷
(N
TOT
) cycle:
and so the phase error increases each cycle by:
This phase error gives an unwanted correction pulse on
the
output as the VCO frequency is too high for the
division ratio in use. The phase error increases as
÷
N
cycles follow each other until eventually the accumulator
overflows and causes a
÷
(N
TOT
+ 1) cycle.
For each
÷
(N
TOT
+ 1) cycle:
Table 7
x (f
COMP
Period) .... (2)
N
TOT
F
f
VCO =
f
COMP
x (N
TOT +
F) .... (1)
MOD
NF
F =
f
FRANC =
f
COMP
x
N
TOT + 1
N
TOT +
F
f
FRANC =
f
COMP
x N
=
f
COMP
x 1+
N
TOT
TOT +
F
N
TOT
N
TOT +
F
( )
x (f
COMP
Period) .... (3)
(N
TOT +
1)
(F - 1)
Phase error = ACC
COMP
Period) .... (4)
N
TOT
x MOD
Iprop (0) = CN x Ibo .... (6)
Charge = ACC x SF
COMP
Period) x Ibo .... (7)
MOD
x (f
COMP
Period) x Iprop (0) .... (5)
N
TOT
x MOD
ACC
相關(guān)PDF資料
PDF描述
ACE9030 Radio Interface and Twin Synthesiser
ACE9040 Audio Processor Advance Information
ACE9050 System Controller and Data Modem(為蜂窩式手機(jī)提供控制和邏輯接口功能的系統(tǒng)控制器和數(shù)據(jù)調(diào)制解調(diào)器)
ACE9050 System Controller and Data Modem Advance Information
ACFA-450 AM CERAMIC FILTERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ACE9030IGFP1N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer
ACE9030IGFP1R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer
ACE9030IGFP2N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer
ACE9030IGFP2R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Parallel-Input Frequency Synthesizer
ACE9030M 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Radio Interface and Twin Synthesiser
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