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參數(shù)資料
| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 281K |
| 代理商： | A6850 |
Altera Corporation
89
a6850 Asynchronous Communications Interface Adapter Data Sheet
Operation
This section describes the following:
I
I
I
I
I
Bus interface operation
Receiver operation
Transmitter operation
Interrupt operation
Reset operation
Bus Interface Operation
A microprocessor or other controlling device accesses the
a6850
through
the bus interface, which provides a direct link to the transmit, receive,
status, and control registers.
The microprocessor interfaces with the
a6850
when the
cs
input is set to
a logic
110
and the
rnw
input is set to a logic low when writing, or a logic
high when reading. The
rs
input then chooses the appropriate register
operation as shown in
Table 7
.
When
cs
,
rnw
, and
rs
are set, access begins when the
e
input transitions
from low to high. The
e
input must be high for at least one
txclk
cycle. In
a read cycle, the data is available through the data output (
do
) bus on the
rising edge of the
e
input. In a write cycle, the data is written on the falling
edge of the
e
input. See
Figure 3
.
Table 7. Register Operations
rnw
rs
Register Operation
0
0
1
1
0
1
0
1
Control register write
Transmit data register write
Status register read
Receive data register read
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