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參數(shù)資料
| 型號(hào)： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁(yè)數(shù)： | 7/15頁(yè) |
| 文件大小： | 281K |
| 代理商： | A6850 |
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Altera Corporation
87
a6850 Asynchronous Communications Interface Adapter Data Sheet
Receiver Data Register Full
Bit 0 of the status register is the
rdrf
bit. When high, the
rdrf
bit indicates
that received data has been transferred into the receiver data register and
is ready to be read by the microprocessor. If the receive interrupt is
enabled, then the
nirq
signal is asserted.
The
rdrf
bit is cleared when either the
nreset
signal is asserted, the
microprocessor reads the receiver data register, or the control register is
set to master reset mode.
Transmitter Data Register Empty
Bit 1 of the status register is the
tdre
bit. When high, the
tdre
bit indicates
that data has been transferred from the transmitter data register to the
output shift register. At this point, the
a6850
is ready to accept a new
transmit data byte. However, if the
ncts
signal is high, the
tdre
bit
remains low regardless of the status of the transmitter data register. Also,
if transmit interrupt is enabled, the
nirq
output is asserted.
The
tdre
bit is cleared when the
nreset
signal is asserted, the
microprocessor writes to the transmitter data register, or the control
register is set to master reset mode.
Data Carrier Detect
Bit 2 of the status register is the
ndcd
bit, which reflects the status of the
ndcd
input. When the
ndcd
input transitions from low to high, the status
bit is set to a logic high. If the receive interupts are enabled, a low on the
nirq
output is produced. Once the
ndcd
bit is set, it remains high
regardless of the state of the
ndcd
input until one of the following
conditions occurs:
I
I
I
The status register is read after reading the receiver data register.
The
nreset
signal is asserted.
The control register is set to master reset mode.
Clear to Send
Bit 3 of the status register is the
ncts
bit, and reflects the status of the
ncts
input. The
nreset
input sets
ncts
bit to a logic high until the next rising
edge of
txclk
.
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