參數(shù)資料
型號(hào)： A67L83181E-10
廠商： AMIC Technology Corporation
英文描述： 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM
中文描述： 256 × 16/18，128K的X 32/36 LVTTL，流通過(guò)數(shù)據(jù)庫(kù)管理員的SRAM
文件頁(yè)數(shù)： 9/19頁(yè)
文件大小： 271K
代理商： A67L83181E-10
A67L83161/A67L83181/
A67L73321/A67L73361 Series
PRELIMINARY (September, 1999, Version 0.1)
8
AMIC Technology, Inc.
Truth Table (Notes 5 - 7)
Operation
Address
Used
None
CE
CE2
CE2
ZZ
ADV/
LD
L
R/
W
BWx
OE
CEN
CLK
I/O
Notes
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Deselected Cycle,
Power-down
Continue Deselect
Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/Dummy READ
(Begin Burst)
Dummy READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE Abort
(Begin Burst)
WRITE Abort
(Continue Burst)
IGNORE Clock
Edge
(Stall)
SLEEP Mode
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3.
OE
may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. Some users may use
OE
when the bus turn-on and turn-off times do not
meet their requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock
Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
BWx
= H means all byte write signals
(
BW1
,
BW2
,
BW3
and
BW4
) are HIGH.
BWx
= L means one or more byte write signals are LOW.
6.
BW1
enables WRITEs to Byte “a” (I/Oa pins);
BW2
enables WRITEs to Byte “b” (I/Ob pins);
BW3
enables WRITEs to
Byte “c” (I/Oc pins);
BW4
enables WRITEs to Byte “d” (I/Od pins).
7. The address counter is incremented for all Continue Burst cycles.
H
X
X
L
X
X
X
L
L
→
H
High-Z
None
X
H
X
L
L
X
X
X
L
L
→
H
High-Z
None
X
X
L
L
L
X
X
X
L
L
→
H
High-Z
None
X
X
X
L
H
X
X
X
L
L
→
H
High-Z
1
External
L
L
H
L
L
H
X
L
L
L
→
H
Q
Next
X
X
X
L
H
X
X
L
L
L
→
H
Q
1,7
External
L
L
H
L
L
H
X
H
L
L
→
H
High-Z
2
Next
X
X
X
L
H
X
X
H
L
L
→
H
High-Z
1,2,7
External
L
L
H
L
L
L
L
X
L
L
→
H
D
3
Next
X
X
X
L
H
X
L
X
L
L
→
H
D
1,3,7
None
L
L
H
L
L
L
H
X
L
L
→
H
High-Z
2,3
Next
X
X
X
L
H
X
H
X
L
L
→
H
High-Z
1,2,3,7
Current
X
X
X
L
X
X
X
X
H
L
→
H
-
4
None
X
X
X
H
X
X
X
X
X
X
High-Z
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A67L83181E-11 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM
A67L83181E-12 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM
A67L8318E-45 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
A67L8318E-5 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
A67L8318E-6 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM
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