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參數(shù)資料
| 型號： | A67L83181E-10 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| 中文描述： | 256 × 16/18，128K的X 32/36 LVTTL，流通過數(shù)據(jù)庫管理員的SRAM |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 271K |
| 代理商： | A67L83181E-10 |
A67L83161/A67L83181/
A67L73321/A67L73361 Series
PRELIMINARY (September, 1999, Version 0.1)
15
AMIC Technology, Inc.
READ/WRITE Timing
Note :
1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional.
3.
CE
represents three signals. When
CE
= 0, it represents
CE
= 0,
CE2
= 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The
most recent data may be from the input data register.
A3
A2
A1
A4
A5
D(A1)
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
: Don't Care
: Undefined
1
2
3
4
5
t
KHKH
6
7
8
9
10
CLK
CEN
CE
ADV/
LD
R/W
BWx
ADDRESS
I/O
COMMAND
A6
A7
D(A2)
D(A2+1)
OE
t
KLKH
t
EVK
H
t
KHE
X
t
KHKL
t
KHCX
t
CVKH
t
KHAX
t
AVKH
t
KHDX
t
DVKH
t
KHQV
t
KHQX1
Q(A3)
t
KHQX
t
GLQX
t
KHQX
t
GHQZ
Q(A6)
D(A5)
Q(A4+1)
t
KHQZ
t
GLQV
Q(A4)
D(A7)
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| A67L8318 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L7332 | 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A67L83181E-11 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L83181E-12 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBA SRAM |
| A67L8318E-45 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L8318E-5 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
| A67L8318E-6 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM |
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