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參數(shù)資料
| 型號： | A65H83181P-7 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| 中文描述： | 128K的× 36 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大小： | 530K |
| 代理商： | A65H83181P-7 |
A65H73361/A65H83181 Series
PRELIMINARY
(February, 1999, Version 2.0)
11
AMIC Technology, Inc.
Timing Diagram (Read Write Cycles)
t
KHAX
t
KLKH
t
KHKL
t
KHKH
CK
SA
SS
SW
G
DQ
t
AVKH
A1
A2
A3
A4
t
KHSX
t
SVKH
Q3
A2
t
KHQV
t
KHQZ
t
KHQX4
t
KHDX
t
KHWX
t
XHWX
t
WVKH
SBW
t
WVKH
t
WVKH
t
KHWX
t
WVKH
t
XHWX
t
GHQZ
Q2
t
DVKH
t
KHDX
t
KHQV
t
DVKH
D4
Q1
D2
NOTES:
1.D2 is the input data write in memory location A2.
2.Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.
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