- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375150 > A65H83181P-7 (AMIC Technology Corporation) 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output PDF資料下載
參數(shù)資料
| 型號(hào)： | A65H83181P-7 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| 中文描述： | 128K的× 36 |
| 文件頁(yè)數(shù)： | 10/21頁(yè) |
| 文件大小： | 530K |
| 代理商： | A65H83181P-7 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
A65H73361/A65H83181 Series
PRELIMINARY
(February, 1999, Version 2.0)
9
AMIC Technology, Inc.
AC Characteristics
(T
J
= 0 to +110
°
C, V
DD
= 3.3V
±
5%)
Parameter
Symbol
-5
-6
-7
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Cycle Time
t
KHKH
5
-
6.0
-
7.0
-
ns
Clock High Pulse Width
t
KHKL
1.5
-
1.5
-
1.5
-
ns
Clock Low Pulse Width
t
KLKH
1.5
-
1.5
-
1.5
-
ns
Clock to Output Valid
t
KHQV
-
2.5
3.0
-
3.5
ns
1
Address Setup Time
t
AVKH
0.5
-
0.5
-
0.5
-
ns
4
Address Hold Time
t
KHAX
1.0
-
1.0
-
1.0
-
ns
4
Sync Select Setup Time
t
SVKH
0.5
-
0.5
-
0.5
-
ns
4
Sync Select Hold Time
t
KHSX
1.0
-
1.0
-
1.0
-
ns
4
Write Enables Setup Time
t
WVKH
0.5
-
0.5
-
0.5
-
ns
4
Write Enables Hold Time
t
KHWX
1.0
-
1.0
-
1.0
-
ns
4
Data In Setup Time
t
DVKH
0.5
-
0.5
-
0.5
-
ns
4
Data In Hold Time
t
KHDX
1.0
-
1.0
-
1.0
-
ns
4
Data Out Hold Time
t
KHQX
0.5
-
0.5
-
0.5
-
ns
1
Clock High to Output High-z
t
KHQZ
-
2.5
-
3.0
-
3.5
ns
1, 2
Clock high to Output Active
t
XHQX4
1.0
-
1.0
-
1.0
-
ns
1, 2
Output Enable to High-z
t
GHQZ
-
2.5
3.0
-
3.5
ns
1, 2
Output Enable to Low-z
t
GLQX
0.5
-
0.5
-
0.5
-
ns
1, 2
Output Enable to Output Valid
t
GLQV
-
2.5
-
3.0
-
3.5
ns
1
Output Enable Setup Time
t
GHKH
0.5
-
0.5
-
0.5
-
ns
1, 3
Output Enable Hold Time
t
KHGX
1.5
-
1.5
-
1.5
-
ns
1, 3
Sleep Mode Recovery Time
t
ZZR
5
-
6
-
7
-
ns
Sleep Mode Enable Time
t
ZZE
-
5
-
6
-
7
ns
1.See AC Test Loading figure on page 8.
2.Transitions are measured
±
200mV from steady state voltage.
3.Output Driver Impedance update specifications for
G
induced updates. Write and Deselect cycles will also induce
Output Driver Updates during High-z.
4.Inuse conditions V
IH
, V
IL
, Trise, Tfall of inputs must be withim 20% of V
IH
, V
IL
, Trise, Tfall of Clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A65H73361SERIES | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| A65H83181SERIES | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| A65H73361 | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| A65H73361P-5 | 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| A66-1 | 10 TO 1000 MHz CASCADABLE AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A65H83181SERIES | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output |
| A-65J | 制造商:Triad Magnetics 功能描述: |
| A65X150VE | 制造商:FACOM 功能描述:SCREWDRIVER 6 5X150 1000V |
| A66 | 制造商:M/A-COM Technology Solutions 功能描述:GAIN BLOCK |
| A6-6 | 制造商:TE Connectivity 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。