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參數(shù)資料
| 型號： | A64S9316G-70I |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 512K X 16 Bit Low Voltage Super RAM |
| 中文描述： | 為512k × 16位低電壓超內(nèi)存 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | A64S9316G-70I |
A64S9316
PRELIMINARY
(July, 2002, Version 0.1)
7
AMIC Technology, Inc.
AC Characteristics
(T
A
= 0
°
C to +70
°
C or -25
°
C to 85
°
C, VCC = 2.7V to 3.1V)
Symbol
Parameter
-70
-85
Unit
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
70
-
85
-
ns
t
SKEW
Address Skew
-
10
-
10
ns
t
AA
Address Access Time
-
70
-
85
ns
t
ACE
Chip Enable Access Time
-
70
-
85
ns
t
BE
Byte Enable Access Time
-
70
-
85
ns
t
OE
Output Enable to Output Valid
-
35
-
45
ns
t
CLZ
Chip Enable to Output in Low Z
10
-
10
-
ns
t
BLZ
Byte Enable to Output in Low Z
5
-
5
-
ns
t
OLZ
Output Enable to Output in Low Z
5
-
5
-
ns
t
CHZ
Chip Disable to Output in High Z
0
25
0
35
ns
t
BHZ
Byte Disable to Output in High Z
0
25
0
35
ns
t
OHZ
Output Disable to Output in High Z
0
25
0
35
ns
t
OH
Output Hold from Address Change
10
-
10
-
ns
t
ASC
Address Setup to CE1 Low
0
-
0
-
ns
t
AHC
Address Hold Time from CE1 High
0
-
0
-
ns
t
CEH
CE1 High Pulse With
10
-
10
-
ns
Write Cycle
t
WC
Write Cycle Time
70
-
85
-
ns
t
SKEW
Address Skew
-
10
-
10
ns
t
CW
Chip Enable to End of Write
60
-
70
-
ns
t
BW
Byte Enable to End of Write
60
-
70
-
ns
t
AS
Address Setup Time
0
-
0
-
ns
t
AW
Address Valid to End of Write
60
-
70
-
ns
t
WP
Write Pulse Width
50
-
55
-
ns
t
WR
Write Recovery Time
0
-
0
-
ns
t
WHZ
Write to Output in High Z
-
20
-
20
ns
t
DW
Data to Write Time Overlap
30
-
35
-
ns
t
DH
Data Hold from Write Time
0
-
0
-
ns
t
OW
Output Active from End of Write
5
-
5
-
ns
t
ASC
Address Setup to CE1 Low
0
-
0
-
ns
t
AHC
Address Hold Time from CE1 High
0
-
0
-
ns
t
CEH
CE1 High Pulse With
10
-
10
-
ns
t
WEH
WE High Pulse With
10
-
10
-
ns
Note: t
CHZ
, t
BHZ
and t
OHZ
and t
WHZ
are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
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