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參數(shù)資料
| 型號： | A64E06161 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 1M X 16 Bit Low Voltage Super RAM |
| 中文描述： | 100萬× 16位低電壓超內(nèi)存 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 310K |
| 代理商： | A64E06161 |
A64E06161
3. Partial Array Refresh (PAR) mode
In this mode, customers can turn off section of A64E06161 in
stand-by mode to save standby current. The A64E06161 is
divided into four 4M sections allowing certain section to be
active. The array partition to be refreshed is determined by
the respective bit in the CR register. When
ZZ
is active low,
only the portion of the array that is set in the CR register is
refreshed and the data is keep at a certain section of
memory. The Partial Array Refresh (PAR) mode is only
available during standby time (
ZZ
low). Once
ZZ
is turned
high, the A64E06161 goes back to operating in full array
refresh. For Partial Array Refresh (PAR) mode to be
activated, the register bit, A4 must be set to a “1” value. To
change the address space of the Partial Array Refresh (PAR)
mode, the CR register must be updated using the CR
register description. If the CR register is not updated after
power on, the A64E06161 will be in its default state and the
whole memory array will be refreshed.
Partial Array Refresh – Entry/Exit
Partial Array Mode/
Deep Power Down Mode
CE or
UB / LB
1us
suspend
t
CDR
t
R
ZZ
Figure 2: Partial Array refresh – Entry/Exit
Partial Array Mode Timings
Parameter
t
ZZWE
Description
Min.
Max.
1
Unit
μs
ZZ LOW to WE LOW
t
CDR
Chip Deselect to ZZ LOW
Operation Recovery Time (Deep Power Down Mode only)
Deep Power Down Mode Time
0
μs
t
R
t
ZZMIN
t
ZZCE
200
1
μs
μs
μs
10
0
ZZ LOW to
CE
LOW
t
ZZBE
ZZ LOW to
LD
UB
/
LOW
0
1
μs
Notes:
1. OE and the data pins are in a “don’t care” state while the device is in Partial Array Mode.
2. All other timing parameters are as shown in the switching characteristics section.
3. t
R
applies only in the Deep Power Down Mode.
4. Temperature Compensated Refresh (TCR) mode
In this mode, the hidden refresh rate can be optimized for the
operating temperature. At higher temperature, the DRAM cell
must be refreshed more often than at lower temperature. By
setting the temperature of operation in CR register, the
refresh rate can be optimized to meet the low standby
current at given operating temperature. There are four
selections (+15
°
C, +45
°
C, +70
°
C, +85
°
C) in the CR register
description.
PRELIMINARY
(November, 2004, Version 0.1)
10
AMIC Technology, Corp.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A64E06161G-70 | 1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-70I | 1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-85 | 1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-85I | 1M X 16 Bit Low Voltage Super RAM |
| A64E16161 | 2M X 16 Bit Low Voltage Super RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A64E06161G-70 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-70I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-85 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit Low Voltage Super RAM |
| A64E06161G-85I | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit Low Voltage Super RAM |
| A64E16161 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:2M X 16 Bit Low Voltage Super RAM |
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