tHCKH Input LOW to HIGH (pad to R-" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX16P-1VQ100M
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 30/64闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 24K GATES 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� SX
LAB/CLB鏁�(sh霉)锛� 1452
杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€鏁�(sh霉)锛� 24000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -55°C ~ 125°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
SX Family FPGAs
1- 32
v3.2
Dedicated (Hardwired) Array Clock Network
tHCKH
Input LOW to HIGH (pad to R-Cell input)
1.9
2.1
2.4
2.8
ns
tHCKL
Input HIGH to LOW (pad to R-Cell input)
1.9
2.1
2.4
2.8
ns
tHPWH
Minimum Pulse Width HIGH
1.4
1.6
1.8
2.1
ns
tHPWL
Minimum Pulse Width LOW
1.4
1.6
1.8
2.1
ns
tHCKSW
Maximum Skew
0.3
0.4
0.5
ns
tHP
Minimum Period
2.7
3.1
3.6
4.2
ns
fHMAX
Maximum Frequency
350
320
280
240
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (light load)
(pad to R-Cell input)
2.4
2.7
3.0
3.5
ns
tRCKL
Input HIGH to LOW (light load)
(pad to R-Cell input)
2.4
2.7
3.1
3.6
ns
tRCKH
Input LOW to HIGH (50% load)
(pad to R-Cell input)
2.7
3.0
3.5
4.1
ns
tRCKL
Input HIGH to LOW (50% load)
(pad to R-Cell input)
2.7
3.1
3.6
4.2
ns
tRCKH
Input LOW to HIGH (100% load)
(pad to R-Cell input)
2.7
3.1
3.5
4.1
ns
tRCKL
Input HIGH to LOW (100% load)
(pad to R-Cell input)
2.8
3.2
3.6
4.3
ns
tRPWH
Min. Pulse Width HIGH
2.1
2.4
2.7
3.2
ns
tRPWL
Min. Pulse Width LOW
2.1
2.4
2.7
3.2
ns
tRCKSW
Maximum Skew (light load)
0.85
0.98
1.1
1.3
ns
tRCKSW
Maximum Skew (50% load)
1.23
1.4
1.6
1.9
ns
tRCKSW
Maximum Skew (100% load)
1.30
1.5
1.7
2.0
ns
TTL Output Module Timing3
tDLH
Data-to-Pad LOW to HIGH
1.6
1.9
2.1
2.5
ns
tDHL
Data-to-Pad HIGH to LOW
1.6
1.9
2.1
2.5
ns
tENZL
Enable-to-Pad, Z to L
2.1
2.4
2.8
3.2
ns
tENZH
Enable-to-Pad, Z to H
2.3
2.7
3.1
3.6
ns
tENLZ
Enable-to-Pad, L to Z
1.4
1.7
1.9
2.2
ns
tENHZ
Enable-to-Pad, H to Z
1.3
1.5
1.7
2.0
ns
Table 1-20 A54SX32 Timing Characteristics (Continued)
(Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70掳C)
Parameter
Description
'鈥�3' Speed
'鈥�2' Speed
'鈥�1' Speed
'Std' Speed
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Note:
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF.
鐩搁棞(gu膩n)PDF璩囨枡
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