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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A54SX16P-1VQ100M |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 15/64闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA SX 24K GATES 100-VQFP |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | SX |
| LAB/CLB鏁�(sh霉)锛� | 1452 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 81 |
| 闁€鏁�(sh霉)锛� | 24000 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -55°C ~ 125°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
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SX Family FPGAs
1- 18
v3.2
Step 3:
Calculate DC Power Dissipation
DC Power Dissipation
PDC = (Istandby) 脳 VCCA + (Istandby) 脳 VCCR + (Istandby) 脳
VCCI + X 脳 VOL 脳 IOL + Y(VCCI 鈥� VOH) 脳 VOH
EQ 1-12
For a rough estimate of DC Power Dissipation, only use
PDC =(Istandby) 脳 VCCA. The rest of the formula provides a
very small number that can be considered negligible.
PDC = (Istandby) 脳 VCCA
PDC = .55 mA 脳 3.3 V
PDC = 0.001815 W
Step 4:
Calculate Total Power Consumption
PTotal = PAC + PDC
PTotal = 1.461 + 0.001815
PTotal = 1.4628 W
Step 5:
Compare Estimated Power Consumption
against Characterized Power Consumption
The estimated total power consumption for this design is
1.46 W. The characterized power consumption for this
design at 200 MHz is 1.0164 W.
Step 1:
Define Terms Used in Formula
VCCA
3.3
Module
Number of logic modules switching
at fm (Used 50%)
m
264
Average logic modules switching rate
fm (MHz) (Guidelines: f/10)
fm
20
Module capacitance CEQM (pF)
CEQM
4.0
Input Buffer
Number of input buffers switching at fn
n1
Average input switching rate fn (MHz)
(Guidelines: f/5)
fn
40
Input buffer capacitance CEQI (pF)
CEQI
3.4
Output Buffer
Number of output buffers switching at fp p1
Average output buffers switching rate
fp(MHz) (Guidelines: f/10)
fp
20
Output buffers buffer capacitance
CEQO (pF)
CEQO
4.7
Output Load capacitance CL (pF)
CL
35
RCLKA
Number of Clock loads q1
q1
528
Capacitance of routed array clock (pF)
CEQCR 1.6
Average clock rate (MHz)
fq1
200
Fixed capacitance (pF)
r1
138
RCLKB
Number of Clock loads q2
q2
0
Capacitance of routed array clock (pF)
CEQCR 1.6
Average clock rate (MHz)
fq2
0
Fixed capacitance (pF)
r2
138
HCLK
Number of Clock loads
s1
0
Variable capacitance of dedicated
array clock (pF)
CEQHV 0.61
5
Fixed capacitance of dedicated
array clock (pF)
CEQHF 96
Average clock rate (MHz)
fs1
0
Step 2:
Calculate Dynamic Power Consumption
VCCA 脳 VCCA
10.89
m 脳 fm 脳 CEQM
0.02112
n 脳 fn 脳 CEQI
0.000136
p 脳 fp 脳 (CEQO+CL)
0.000794
0.5 (q1 脳 CEQCR 脳 fq1) + (r1 脳 fq1)
0.11208
0.5(q2 脳 CEQCR 脳 fq2) + (r2 脳 fq2)0
0.5 (s1 脳 CEQHV 脳 fs1) + (CEQHF 脳 fs1)0
PAC = 1.461 W
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A54SX16P-1VQG100M | IC FPGA SX 24K GATES 100-VQFP |
| ASC49DREN-S734 | CONN EDGECARD 98POS .100 EYELET |
| M1AFS1500-2FG676I | IC FPGA 8MB FLASH 1.5M 676-FBGA |
| AFS1500-2FGG676I | IC FPGA 8MB FLASH 1.5M 676-FBGA |
| AFS1500-2FG676I | IC FPGA 8MB FLASH 1.5M 676-FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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