Table 2-19 A54SX08A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A54SX16A-2TQ144
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 48/108闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA SX 24K GATES 144-TQFP
妯欐簴鍖呰锛� 60
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 1452
杓稿叆/杓稿嚭鏁�(sh霉)锛� 113
闁€鏁�(sh霉)锛� 24000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 144-TQFP锛�20x20锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�鐣跺墠绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�
SX-A Family FPGAs
2- 24
v5.3
Table 2-19 A54SX08A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70掳C)
Parameter
Description
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
3.3 V PCI Output Module Timing1
tDLH
Data-to-Pad Low to High
2.2
2.4
2.9
4.0
ns
tDHL
Data-to-Pad High to Low
2.3
2.6
3.1
4.3
ns
tENZL
Enable-to-Pad, Z to L
1.7
1.9
2.2
3.1
ns
tENZH
Enable-to-Pad, Z to H
2.2
2.4
2.9
4.0
ns
tENLZ
Enable-to-Pad, L to Z
2.8
3.2
3.8
5.3
ns
tENHZ
Enable-to-Pad, H to Z
2.3
2.6
3.1
4.3
ns
dTLH
2
Delta Low to High
0.03
0.04
0.045
ns/pF
dTHL
2
Delta High to Low
0.015
0.025
ns/pF
3.3 V LVTTL Output Module Timing3
tDLH
Data-to-Pad Low to High
3.0
3.4
4.0
5.6
ns
tDHL
Data-to-Pad High to Low
3.0
3.3
3.9
5.5
ns
tDHLS
Data-to-Pad High to Low鈥攍ow slew
10.4
11.8
13.8
19.3
ns
tENZL
Enable-to-Pad, Z to L
2.6
2.9
3.4
4.8
ns
tENZLS
Enable-to-Pad, Z to L鈥攍ow slew
18.9
21.3
25.4
34.9
ns
tENZH
Enable-to-Pad, Z to H
3
3.4
4
5.6
ns
tENLZ
Enable-to-Pad, L to Z
3.3
3.7
4.4
6.2
ns
tENHZ
Enable-to-Pad, H to Z
3
3.3
3.9
5.5
ns
dTLH
2
Delta Low to High
0.03
0.04
0.045
ns/pF
dTHL
2
Delta High to Low
0.015
0.025
ns/pF
dTHLS
2
Delta High to Low鈥攍ow slew
0.053
0.067
0.073
0.107
ns/pF
Notes:
1. Delays based on 10 pF loading and 25
惟 resistance.
2. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI 鈥� 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
3. Delays based on 35 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A54SX16A-1TQ144I IC FPGA SX 24K GATES 144-TQFP
EMC49DRAN CONN EDGECARD 98POS R/A .100 SLD
A40MX04-2VQG80I IC FPGA MX SGL CHIP 6K 80-VQFP
EMC49DRAH CONN EDGECARD 98POS R/A .100 SLD
AMC25DRYI CONN EDGECARD 50POS .100 DIP SLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A54SX16A-2TQ144I 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 144-TQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A54SX16A-2TQG100 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 100-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A54SX16A-2TQG100I 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 100-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A54SX16A-2TQG144 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 144-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A54SX16A-2TQG144I 鍔熻兘鎻忚堪:IC FPGA SX 24K GATES 144-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:SX-A 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�