Table 2-39 A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A54SX08A-1FG144
寤�(ch菐ng)鍟嗭細 Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 77/108闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA SX 12K GATES 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 111
闁€(m茅n)鏁�(sh霉)锛� 12000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
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宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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SX-A Family FPGAs
2- 50
v5.3
Table 2-39 A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 2.3 V, TJ = 70掳C)
Parameter
Description
鈥�3 Speed1
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
2.5 V LVCMOS Output Module Timing2, 3
tDLH
Data-to-Pad Low to High
3.9
4.5
5.1
6.0
8.4
ns
tDHL
Data-to-Pad High to Low
3.1
3.6
4.1
4.8
6.7
ns
tDHLS
Data-to-Pad High to Low鈥攍ow slew
12.7
14.6
16.5
19.4
27.2
ns
tENZL
Enable-to-Pad, Z to L
2.4
2.8
3.2
3.7
5.2
ns
tENZLS
Data-to-Pad, Z to L鈥攍ow slew
11.8
13.7
15.5
18.2
25.5
ns
tENZH
Enable-to-Pad, Z to H
3.9
4.5
5.1
6.0
8.4
ns
tENLZ
Enable-to-Pad, L to Z
2.1
2.5
2.8
3.3
4.7
ns
tENHZ
Enable-to-Pad, H to Z
3.1
3.6
4.1
4.8
6.7
ns
dTLH
4
Delta Low to High
0.031
0.037
0.043
0.051
0.071
ns/pF
dTHL
4
Delta High to Low
0.017
0.023
0.037
ns/pF
dTHLS
4
Delta High to Low鈥攍ow slew
0.057
0.06
0.071
0.086
0.117
ns/pF
Note:
1. All 鈥�3 speed grades have been discontinued.
2. Delays based on 35 pF loading.
3. The equivalent IO Attribute settings for 2.5 V LVCMOS is 2.5 V LVTTL in the software.
4. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI 鈥� 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
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