- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4462 > A54SX08-1VQ100 (Microsemi SoC)IC FPGA SX 12K GATES 100-VQFP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A54SX08-1VQ100 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 59/64闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA SX 12K GATES 100-VQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | SX |
| LAB/CLB鏁�(sh霉)锛� | 768 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 81 |
| 闁€(m茅n)鏁�(sh霉)锛� | 12000 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)鐣�(d膩ng)鍓嶇59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)
54SX Family FPGAs
2- 24
v3.2
144-Pin FBGA
Pin
Number
A54SX08
Function
A1
I/O
A2
I/O
A3
I/O
A4
I/O
A5
VCCA
A6
GND
A7
CLKA
A8
I/O
A9
I/O
A10
I/O
A11
I/O
A12
I/O
B1
I/O
B2
GND
B3
I/O
B4
I/O
B5
I/O
B6
I/O
B7
CLKB
B8
I/O
B9
I/O
B10
I/O
B11
GND
B12
I/O
C1
I/O
C2
I/O
C3
TCK, I/O
C4
I/O
C5
I/O
C6
PRA, I/O
C7
I/O
C8
I/O
C9
I/O
C10
I/O
C11
I/O
C12
I/O
D1
I/O
D2
VCCI
D3
TDI, I/O
D4
I/O
D5
I/O
D6
I/O
D7
I/O
D8
I/O
D9
I/O
D10
I/O
D11
I/O
D12
I/O
E1
I/O
E2
I/O
E3
I/O
E4
I/O
E5
TMS
E6
VCCI
E7
VCCI
E8
VCCI
E9
VCCA
E10
I/O
E11
GND
E12
I/O
F1
I/O
F2
I/O
F3
VCCR
F4
I/O
F5
GND
F6
GND
F7
GND
F8
VCCI
F9
I/O
F10
GND
F11
I/O
F12
I/O
144-Pin FBGA
Pin
Number
A54SX08
Function
G1
I/O
G2
GND
G3
I/O
G4
I/O
G5
GND
G6
GND
G7
GND
G8
VCCI
G9
I/O
G10
I/O
G11
I/O
G12
I/O
H1
I/O
H2
I/O
H3
I/O
H4
I/O
H5
VCCA
H6
VCCA
H7
VCCI
H8
VCCI
H9
VCCA
H10
I/O
H11
I/O
H12
VCCR
J1
I/O
J2
I/O
J3
I/O
J4
I/O
J5
I/O
J6
PRB, I/O
J7
I/O
J8
I/O
J9
I/O
J10
I/O
J11
I/O
J12
VCCA
144-Pin FBGA
Pin
Number
A54SX08
Function
K1
I/O
K2
I/O
K3
I/O
K4
I/O
K5
I/O
K6
I/O
K7
GND
K8
I/O
K9
I/O
K10
GND
K11
I/O
K12
I/O
L1
GND
L2
I/O
L3
I/O
L4
I/O
L5
I/O
L6
I/O
L7
HCLK
L8
I/O
L9
I/O
L10
I/O
L11
I/O
L12
I/O
M1
I/O
M2
I/O
M3
I/O
M4
I/O
M5
I/O
M6
I/O
M7
VCCA
M8
I/O
M9
I/O
M10
I/O
M11
TDO, I/O
M12
I/O
144-Pin FBGA
Pin
Number
A54SX08
Function
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A54SX08-1VQG100 | IC FPGA SX 12K GATES 100-VQFP |
| A42MX16-PQG208 | IC FPGA MX SGL CHIP 24K 208-PQFP |
| A42MX16-PQ208 | IC FPGA MX SGL CHIP 24K 208-PQFP |
| A42MX09-3PQ100 | IC FPGA MX SGL CHIP 14K 100-PQFP |
| EMC55DRSN-S273 | CONN EDGECARD 110PS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A54SX08-1VQ100I | 鍔熻兘鎻忚堪:IC FPGA SX 12K GATES 100-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄ｅ垪锛� 绯诲垪:SX 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€(m茅n)鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A54SX08-1VQ100M | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA) |
| A54SX08-1VQ208 | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs |
| A54SX08-1VQ208I | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs |
| A54SX08-1VQ208M | 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:54SX Family FPGAs |
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