參數(shù)資料
型號: A43P26161V-95F
廠商: AMIC Technology Corporation
英文描述: 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
中文描述: 100萬× 16位× 4個銀行的低功耗同步DRAM
文件頁數(shù): 10/44頁
文件大小: 1122K
代理商: A43P26161V-95F
A43P26161
PRELIMINARY
(July, 2005, Version 1.1)
9
AMIC Technology, Corp.
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BS1
BS0
A11,A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
0
0
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 3) (Note 1) (Note 2)
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1 A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
0
0
1
-
1
Interleave
0
0
1
2
2
1
0
0
1
0
2
0
1
0
4
4
1
1
Vendor
Use
Only
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
A9
Length
1
0
1
Reserved
1
0
1
Reserved
Reserved
0
Burst
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
Single Bit
1
1
1
Reserved
1
1
1
256(Full)
Reserved
Note :
1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
3. BS0, BS1 must be 0,0 to select the Mode Register (vs. the Extended Mode Register).
Extended Mode Register Table
BS1
1
BS0
0
A11, A10
All have to be set to “0”
A9
A8
A7
A6
A5
A4
A3
A2
A1
PASR
A0
Address Bus (Ax)
DS
TCSR
(Note)
Driver Strength
Temperature-Compensated Self-Refresh:
Partial-Array Self Refresh:
Driver Strength
A4
A3
Max. Case Temp.
A6
0
0
1
A5
0
1
0
Driver Strength
Full
1/2
1/4
0
0
1
1
0
1
0
1
70
°
C
45
°
C
15
°
C
85
°
C
A2
A1
A0
Banks to be Self-Refreshed
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
All banks
Bank A, Bank B
Bank A
Reserved
Reserved
1/2 of Bank A
1/4 of Bank A
Reserved
Note:
BS1 and BS0 must be 1, 0 to select the Extended Mode Register (vs. the Mode Register)
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