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參數(shù)資料
| 型號(hào)： | A43P26161G-95 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| 中文描述： | 100萬× 16位× 4個(gè)銀行的低功耗同步DRAM |
| 文件頁數(shù)： | 7/44頁 |
| 文件大?。?/td> | 1122K |
| 代理商： | A43P26161G-95 |
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A43P26161
PRELIMINARY
(July, 2005, Version 1.1)
6
AMIC Technology, Corp.
AC Operating Test Conditions
(VDD = 2.3V~2.7V, T
A
= 0oC to +70oC for commercial or T
A
=-40oC to +85oC for extended)
Parameter
Value
Unit
AC input levels
0.9 x VDDQ/0.2
V
Input timing measurement reference level
0.5 x VDDQ
V
Input rise and all time (See note3)
tr/tf = 1/1
ns
Output timing measurement reference level
0.5 x VDDQ
V
Output load condition
See Fig.2
Output
500
500
(Fig. 1) DC Output Load Circuit
Z
O
=50
OUTPUT
50
V
TT
=0.5V x VDDQ
30pF
(Fig. 2) AC Output Load Circuit
VDDQ
30pF
V
OH
(DC) = VDDQ-0.2V, I
OH
= -0.1mA
V
OL
(DC) = 0.2V, I
OL
= 0.1mA
AC Characteristics
(AC operating conditions unless otherwise noted)
-75
-95
Symbol
Parameter
Min
Max
Min
Max
Unit
Note
CL=3
7.5
9.5
t
CC
CLK cycle time
CL=2
12
1000
15
1000
ns
1
CL=3
-
6
-
7
t
SAC
CLK to valid
Output delay
CL=2
-
9
-
8
ns
1,2
t
OH
Output data hold time
2.5
-
2.5
-
ns
2
CL=3
3
-
3.5
-
t
CH
CLK high pulse width
CL=2
CL=3
3
3
-
-
3.5
3.5
-
-
ns
3
t
CL
CLK low pulse width
CL=2
3
-
3.5
-
ns
3
CL=3
2
-
2
-
t
SS
Input setup time
CL=2
2
-
2
-
ns
3
t
SH
Input hold time
1.5
-
1.5
-
ns
3
t
SLZ
CLK to output in Low-Z
1
-
1
-
ns
2
CL=3
-
6
-
7
t
SHZ
CLK to output in Hi-Z
CL=2
-
8
-
8
ns
CL=CAS Latency.
*All AC parameters are measured from half to half.
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e.,
[
(tr + tf)/2-1
]
ns should be added to the parameter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43P26161G-95F | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95U | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95UF | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161V | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161V-75 | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43P26161G-95F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161V | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161V-75 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
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