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參數(shù)資料
| 型號： | A43P26161G-75F |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | OSC 3.3V SMT 7X5 CMOS |
| 中文描述： | 100萬× 16位× 4個銀行的低功耗同步DRAM |
| 文件頁數(shù)： | 9/44頁 |
| 文件大小： | 1122K |
| 代理商： | A43P26161G-75F |
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A43P26161
PRELIMINARY
(July, 2005, Version 1.1)
8
AMIC Technology, Corp.
Simplified Truth Table
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BS0
BS1
A10
/AP
A9~A0,
A11
Notes
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Extended Mode Register Set
H
X
L
L
L
L
L
OP CODE
1,2
Auto Refresh
H
L
3
Entry
H
L
L
L
H
X
X
3
L
H
H
H
3
Refresh
Self
Refresh
Exit
L
H
H
L
X
L
X
H
X
H
X
X
3
4
Bank Active & Row Addr.
H
X
X
V
Row Addr.
Auto Precharge Disable
L
H
L
H
4
4,5
4
4,5
6
7
Read &
Column Addr. Auto Precharge Enable
Auto Precharge Disable
Write &
Column Addr. Auto Precharge Enable
Burst Stop
Bank Selection
Precharge
Both Banks
H
X
L
H
L
H
X
V
Column
Addr.
H
X
L
H
L
L
X
V
Column
Addr.
H
X
L
H
H
L
X
X
V
X
L
H
H
X
L
L
H
L
X
X
L
H
X
L
H
L
H
H
X
X
H
X
V
X
X
H
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
H
V
X
L
H
L
X
H
X
H
X
H
X
L
X
No Operation Command
H
X
X
X
Deep Power Down Entry
Deep Power Down Exit
Note :
1. OP Code: Operand Code
A0~A11, BS0, BS1: Program keys. (@MRS, EMRS)
2. MRS can be issued only when all banks are at precharge state.
A new command can be issued after 2 clock cycle of MRS, EMRS.
3. Auto refresh functions is same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only when all banks are at precharge state.
4. BS0, BS1 : Bank select address.
If both BS1 and BS0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BS1 is “Low” and BS0 is “High” at read, write, row active and precharge, bank B is selected.
If both BS1 is “High” and BS0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BS1 and BS0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BS1 and BS0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0)
but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
7. After Deep Power Down mode exit, a full new initialization of the memory device is mandatory.
H
L
L
H
X
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A43P26161G-75U | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-75UF | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95 | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95F | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95U | 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A43P26161G-75U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-75UF | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95 | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95F | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
| A43P26161G-95U | 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM |
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