參數(shù)資料
型號(hào): A43P26161G-75F
廠商: AMIC Technology Corporation
英文描述: OSC 3.3V SMT 7X5 CMOS
中文描述: 100萬(wàn)× 16位× 4個(gè)銀行的低功耗同步DRAM
文件頁(yè)數(shù): 25/44頁(yè)
文件大?。?/td> 1122K
代理商: A43P26161G-75F
Read & Write Cycle at Same Bank @Burst Length=4
A43P26161
PRELIMINARY
(July, 2005, Version 1.1)
24
AMIC Technology, Corp.
High
t
RC
t
RCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BS0
WE
DQM
DQ
(CL = 2)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note 1
*Note 2
Ra
Ca0
Rb
Cb0
Ra
Rb
A10/AP
Qa0
t
OH
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
RAC
*Note 3
t
SAC
t
SHZ
*Note 4
Qa0
t
OH
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
RAC
t
SAC
*Note 3
t
SHZ
*Note 4
t
RDL
Write
(A-Bank)
DQ
(CL = 3)
BS1
t
RDL
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after t
SHZ
from the clock.
3. Access time from Row address. t
CC
*(t
RCD
+ CAS latency-1) + t
SAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
相關(guān)PDF資料
PDF描述
A43P26161G-75U 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-75UF 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95F 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95U 1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A43P26161G-75U 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-75UF 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95F 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
A43P26161G-95U 制造商:AMICC 制造商全稱:AMIC Technology 功能描述:1M X 16 Bit X 4 Banks Low Power Synchronous DRAM