參數(shù)資料
型號: A43L8316V-8
廠商: AMIC Technology Corporation
英文描述: 128K X 16 Bit X 2 Banks Synchronous DRAM
中文描述: 128K的× 16位× 2銀行同步DRAM
文件頁數(shù): 9/45頁
文件大小: 1395K
代理商: A43L8316V-8
A43L8316
Preliminary (April, 2000, Version 1.0)
8
AMIC Technology, Inc.
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
CAS
Latency
-7
-8
-10
Unit
Note
3
t
RRD(min)
Row active to row active delay
2
2
2
2
CLK
1
3
3
t
RCD(min)
RAS
to
CAS
delay
2
2
2
3
CLK
1
3
3
t
RP(min)
Row precharge time
2
2
2
3
CLK
1
3
7
6
t
RAS(min)
2
5
5
6
CLK
1
3
t
RAS(max)
Row active time
2
100
100
120
μ
s
3
10
9
t
RC(min)
Row cycle time
2
7
7
10
CLK
1
3
t
CDL(min)
Last data in new col. Address delay
2
1
1
1
CLK
2
3
t
RDL(min)
Last data in row precharge
2
1
1
1
CLK
2
3
t
BDL(min)
Last data in to burst stop
2
1
1
1
CLK
2
3
t
CCD(min)
Col. Address to col. Address delay
2
1
1
1
CLK
3
2
2
2
CLK
4
Number of valid output data
2
1
1
1
CLK
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
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