參數(shù)資料
型號(hào): A43L8316AV-5.5
廠(chǎng)商: AMIC Technology Corporation
英文描述: 128K X 16 Bit X 2 Banks Synchronous DRAM
中文描述: 128K的× 16位× 2銀行同步DRAM
文件頁(yè)數(shù): 27/45頁(yè)
文件大?。?/td> 1008K
代理商: A43L8316AV-5.5
A43L8316A
(September, 2003, Version 1.0)
26
AMIC Technology, Corp.
Page Read & Write Cycle at Same Bank @Burst Length=4
t
RDL
High
t
RCD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
WE
DQM
DQ
(CL=2)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note 2
Ra
Ca0
Cb0
Cc0
Ra
A8/AP
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
Qa0
Qa1
Qb0
Write
(A-Bank)
Cd0
t
CDL
*Note 2
*Note1
*Note3
Dc0
Dc1
Dd0
Dd1
Read
(A-Bank)
Write
(A-Bank)
DQ
(CL=3)
*Note :
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, t
RDL
before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
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