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參數(shù)資料
| 型號： | A43L8316AV-5.5 |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 128K X 16 Bit X 2 Banks Synchronous DRAM |
| 中文描述： | 128K的× 16位× 2銀行同步DRAM |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 1008K |
| 代理商： | A43L8316AV-5.5 |
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A43L8316A
(September, 2003, Version 1.0)
9
AMIC Technology, Corp.
Simplified Truth Table
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA A8/
AP
A7~A0 Notes
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Auto Refresh
H
L
3
3
3
Entry
H
L
L
L
H
X
X
L
H
H
H
Refresh
Self
Refresh
Exit
L
H
H
L
X
L
X
H
X
H
X
X
3
4
Bank Active & Row Addr.
H
X
X
V
Row Addr.
Auto Precharge Disable
L
H
L
H
4
4,5
4
4,5
6
7
Read &
Column Addr. Auto Precharge Enable
Auto Precharge Disable
Write &
Column Addr. Auto Precharge Enable
Burst Stop
Bank Selection
Precharge
Both Banks
H
X
L
H
L
H
X
V
Column
Addr.
H
X
L
H
L
L
X
V
Column
Addr.
H
X
L
H
H
L
X
X
V
X
L
H
H
X
L
L
H
L
X
X
L
H
X
L
H
L
H
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
Entry
H
L
X
Precharge Power Down Mode
Exit
L
H
X
X
DQM
H
V
X
L
H
H
X
H
X
No Operation Command
H
X
X
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note :
1. OP Code : Operand Code
A0~A8/AP,BA : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
4. BA : Bank select address.
If “Low” at read, write, Row active and precharge, bank A is selected.
If “High” at read, write, Row active and precharge, bank B is selected.
If A8/AP is “High” at Row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read write command cannot be issued.
Another bank read write command can be issued at every burst length.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
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