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40MX and 42MX FPGA Families
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PCI System Timing Specification
parameters for the MX PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI
Target and Target+DMA Master interface. Contact your Microsemi sales representative for more
details.
Table 1-26 Clock Specification for 33 MHz PCI
Symbol
Parameter
PCI
A42MX24
A42MX36
Units
Min.
Max.
Min.
Max.
Min.
Max.
tCYC
CLK Cycle Time
30
–4.0–4.0
–
ns
tHIGH
CLK High Time
11
–1.9–1.9
–
ns
tLOW
CLK Low Time
11
–1.9–1.9
–
ns
Table 1-27 Timing Parameters for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
Parameter
Min.
Max. Min. Max. Min. Max. Units
tVAL
CLK to Signal Valid—Bused Signals
2
11
2.0
9.0
2.0
9.0
ns
tVAL(PTP) CLK to Signal Valid—Point-to-Point
2 2
12
2.0
9.0
2.0
9.0
ns
tON
Float to Active
2
–
2.0
4.0
2.0
4.0
ns
tOFF
Active to Float
–
28
–
8.31
–8.31
ns
tSU
Input Set-Up Time to CLK—Bused Signals
7
–
1.5
–
1.5
–
ns
tSU(PTP) Input Set-Up Time to CLK—Point-to-Point
10, 122
–
1.5
–
1.5
–
ns
tH
Input Hold to CLK
0
–
0
–
0
–
ns
Notes:
1. TOFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional
10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12.