The MX family of FPGAs is fully supported by Libero
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A40MX04-2PL84
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 56/142闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA MX SGL CHIP 6K 84-PLCC
妯欐簴鍖呰锛� 16
绯诲垪锛� MX
杓稿叆/杓稿嚭鏁�(sh霉)锛� 69
闁€鏁�(sh霉)锛� 6000
闆绘簮闆诲锛� 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 84-LCC锛圝 褰㈠紩绶氾級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 84-PLCC锛�29.31x29.31锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�鐣跺墠绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�
40MX and 42MX FPGA Families
1- 16
R e v i sio n 1 1
Development Tool Support
The MX family of FPGAs is fully supported by Libero Integrated Design Environment (IDE). Libero IDE
is a design management environment, seamlessly integrating design tools while guiding the user through
the design flow, managing all design and log files, and passing necessary design data among tools.
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim HDL
Simulator from Mentor Graphics, and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for
FPGA development, including timing-driven place-and-route, and a world-class integrated static timing
analyzer and constraints editor.
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi鈥檚 integrated verification and logic analysis
tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Microsemi鈥檚 Libero software is compatible with the most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synopsys, and Cadence Design Systems.
Refer to the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for
further information on licensing and current operating system support.
Related Documents
Application Notes
User鈥檚 Guides and Manuals
Miscellaneous
5.0 V Operating Conditions
Table 1-6
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
VCC
DC Supply Voltage
鈥�0.5 to +7.0
V
VI
Input Voltage
鈥�0.5 to VCC+0.5
V
VO
Output Voltage
鈥�0.5 to VCC+0.5
V
鐩搁棞PDF璩囨枡
PDF鎻忚堪
APA150-FGG144 IC FPGA PROASIC+ 150K 144-FBGA
APA150-FG144 IC FPGA PROASIC+ 150K 144-FBGA
AMM25DRSD-S288 CONN EDGECARD 50POS .156 EXTEND
RSA50DRMI CONN EDGECARD 100POS .125 SQ WW
RMA50DRMI CONN EDGECARD 100POS .125 SQ WW
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鍙冩暩(sh霉)鎻忚堪
A40MX04-2PL84I 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:MX 妯欐簴鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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