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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | A40MX02-1VQ80 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 114/142闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA MX SGL CHIP 3K 80-VQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | MX |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 闁€鏁�(sh霉)锛� | 3000 |
| 闆绘簮闆诲锛� | 3 V ~ 3.6 V锛�4.75 V ~ 5.25 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
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40MX and 42MX FPGA Families
Re vi s i on 11
1 - 69
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
2.4
2.7
3.1
3.6
5.1
ns
tDHL
Data-to-Pad LOW
2.8
3.2
3.6
4.2
5.9
ns
tENZH
Enable Pad Z to HIGH
2.5
2.8
3.2
3.8
5.3
ns
tENZL
Enable Pad Z to LOW
2.8
3.1
3.5
4.2
5.9
ns
tENHZ
Enable Pad HIGH to Z
5.2
5.7
6.5
7.6
10.7
ns
tENLZ
Enable Pad LOW to Z
4.8
5.3
6.0
7.1
9.9
ns
tGLH
G-to-Pad HIGH
2.9
3.2
3.6
4.3
6.0
ns
tGHL
G-to-Pad LOW
2.9
3.2
3.6
4.3
6.0
ns
tLSU
I/O Latch Output Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.6
6.1
6.9
8.1
11.4
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
10.6
11.8
13.4
15.7
22.0
ns
dTLH
Capacitive Loading, LOW to HIGH
0.04
0.05
0.07 ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.03
0.04
0.06 ns/pF
Table 1-36 A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70掳C)
鈥�3 Speed
鈥�2 Speed
鈥�1 Speed
Std Speed
鈥揊 Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| ESC60DRYI-S734 | CONN EDGECARD 120PS DIP .100 SLD |
| A40MX02-VQ80I | IC FPGA MX SGL CHIP 3K 80-VQFP |
| ABC35DRAI-S734 | CONN EDGECARD 70POS .100 R/A PCB |
| A40MX02-1VQG80 | IC FPGA MX SGL CHIP 3K 80-VQFP |
| RBB92DHBS-S329 | EDGECARD PCI 184PS .050 R/A 3.3V |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A40MX02-1VQ80I | 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 80-VQFP RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
| A40MX02-1VQ80M | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 3K GATES 295 CELLS 96MHZ/160MHZ 0.45UM 3.3V/5V 80VQFP - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 57 I/O 80VQFP |
| A40MX02-1VQG80 | 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 80-VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
| A40MX02-1VQG80I | 鍔熻兘鎻忚堪:IC FPGA MX SGL CHIP 3K 80-VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:MX 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛� |
| A40MX02-1VQG80M | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA 3K GATES 295 CELLS 96MHZ/160MHZ 0.45UM 3.3V/5V 80VQFP - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 57 I/O 80VQFP |
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