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參數(shù)資料
| 型號(hào)： | A3PN250-ZVQG100I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 20/114頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA NANO 250K GATES 100-VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ProASIC3 nano |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 68 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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ProASIC3 nano Flash FPGAs
Revision 11
1-7
I/Os with Advanced I/O Standards
ProASIC3 nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V).
The I/Os are organized into banks, with two, three, or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of various single-data-rate applications for all versions of nano devices and double-data-
rate applications for the A3PN060, A3PN125, and A3PN250 devices.
ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support
cold-sparing and Schmitt trigger.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
ProASIC3 nano devices support JEDEC-defined wide range I/O operation. ProASIC3 nano supports the
JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to
3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the flexibility
to easily run custom voltage applications.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-6 on page 1-8).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
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