2-2 Revision 11 Table 2-2 Recommended Operating Conditions
參數(shù)資料
型號： A3PN250-ZVQG100
廠商： Microsemi SoC
文件頁數(shù)： 23/114頁
文件大?。?/td> 0K
描述： IC FPGA NANO 250K GATES 100-VQFP
標準包裝： 90
系列： ProASIC3 nano
RAM 位總計： 36864
輸入/輸出數(shù)： 68
門數(shù)： 250000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
ProASIC3 nano DC and Switching Characteristics
2-2
Revision 11
Table 2-2 Recommended Operating Conditions 1, 2
Symbol
Parameter
Extended
Commercial
Industrial
Units
TA
Ambient temperature
–20 to +70 2
–40 to +85 2
°C
TJ
Junction temperature
–20 to +85
–40 to +100
°C
VCC 3
1.5 V DC core supply voltage
1.425 to 1.575
V
VJTAG
JTAG DC voltage
1.4 to 3.6
V
VPUMP 4
Programming voltage
Programming Mode4
3.15 to 3.45
V
Operation 5
0 to 3.6
V
VCCPLL 6
Analog power supply (PLL)
1.5 V DC core supply voltage 3 1.425 to 1.575
1.425 to 1.575
V
VCCI
and
VMV 7
1.5 V DC supply voltage
1.425 to 1.575
V
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
V
3.3 V Wide Range supply voltage 8
2.7 to 3.6
V
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi
recommends that the user follow best design practices using Microsemi’s timing and power simulation tools.
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
standard are given in Table 2-14 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank.
4. The programming temperature range supported is Tambient = 0°C to 85°C.
5. VPUMP can be left floating during operation (not programming mode).
6. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions and Packaging" chapter for further information.
7. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions and Packaging" chapter for
further information.
8. 3.3 V Wide Range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
Table 2-3 Flash Programming Limits – Retention, Storage and Operating Temperature1
Product
Grade
Programming
Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C) 2
Maximum Operating
Junction Temperature TJ (°C) 2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating
conditions and absolute limits.
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A3PN250-ZVQG100I 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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