參數(shù)資料
型號: A3PN125-Z1VQ100
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件頁數(shù): 70/100頁
文件大小: 3284K
代理商: A3PN125-Z1VQ100
ProASIC3 nano DC and Switching Characteristics
Ad vance v0.2
2-57
Timing Characteristics
Table 2-70 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tAS
Address Setup time
0.25
0.28
0.33
ns
tAH
Address Hold time
0.00
ns
tENS
REN_B, WEN_B Setup time
0.14
0.16
0.19
ns
tENH
REN_B, WEN_B Hold time
0.10
0.11
0.13
ns
tBKS
BLK_B Setup time
0.23
0.27
0.31
ns
tBKH
BLK_B Hold time
0.02
ns
tDS
Input data (DI) Setup time
0.18
0.21
0.25
ns
tDH
Input data (DI) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
1.79
2.03
2.39
ns
Clock High to New Data Valid on DO (flow-through, WMODE = 1)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
0.89
1.02
1.20
ns
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same
address; applicable to closing edge
0.33
0.28
0.25
ns
tC2CWWH
Address collision clk-to-clk delay for reliable write after write on same
address; applicable to rising edge
0.30
0.26
0.23
ns
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on
same address; applicable to opening edge
0.45
0.38
0.34
ns
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on
same address; applicable to opening edge
0.49
0.42
0.37
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow through)
0.92
1.05
1.23
ns
RESET_B Low to Data Out Low on DO (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET_B Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET_B Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency
310
272
231
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating
values.
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