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ProASIC3 nano DC and Switching Characteristics
2-14
Revision 11
Figure 2-4 Output Buffer Model and Delays (example)
tDP
(R)
PAD
VOL
tDP
(F)
Vtrip
VOH
VCC
D
50%
VCC
0 V
DOUT
50%
0 V
tDOUT
(R)
tDOUT
(F)
From Array
PAD
tDP
Std
Load
D
CLK
Q
I/O Interface
DOUT
D
tDOUT
tDP = MAX(tDP(R), tDP(F))
tDOUT = MAX(tDOUT(R), tDOUT(F))
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