參數(shù)資料
型號： A3PN125-2VQG100
元件分類： FPGA
英文描述： FPGA, 3072 CLBS, 125000 GATES, PQFP100
封裝： 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件頁數(shù)： 14/106頁
文件大?。?/td> 3324K
代理商： A3PN125-2VQG100
R e visio n 8
2 -1
2 – ProASIC3 nano DC and Switching Characteristics
General Specifications
The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing,
and hot-swap I/O capability. Refer to the ordering information in the ProASIC3 nano Product Brief for
more information.
DC and switching characteristics for –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA
specifications. Some restrictions might be added and will be reflected in future revisions of this
document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the Recommended Operating Conditions specified in
Table 2-2 on page 2-2 is not implied.
Table 2-1 Absolute Maximum Ratings
Symbol
Parameter
Limits
Units
VCC
DC core supply voltage
–0.3 to 1.65
V
VJTAG
JTAG DC voltage
–0.3 to 3.75
V
VPUMP
Programming voltage
–0.3 to 3.75
V
VCCPLL
Analog power supply (PLL)
–0.3 to 1.65
V
VCCI
DC I/O output buffer supply voltage
–0.3 to 3.75
V
VI
I/O input voltage
–0.3 V to 3.6 V
V
TSTG
1
Storage temperature
–65 to +150
°C
TJ
1
Junction temperature
+125
°C
Notes:
1. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating
limits, refer to Table 2-2 on page 2-2.
2. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may
undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3.
相關(guān)PDF資料
PDF描述
A3PN125-VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQ100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-VQG100 FPGA, 3072 CLBS, 125000 GATES, PQFP100
A3PN125-Z1VQ100I FPGA, 3072 CLBS, 125000 GATES, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PN125-2VQG100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-DIELOT 制造商:Microsemi Corporation 功能描述:A3PN125-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film
A3PN125-VQ100 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-VQ100I 功能描述:IC FPGA NANO 125K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PN125-VQG100 功能描述:IC FPGA NANO 1024MAC 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
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