
ProASIC3E Flash Family FPGAs
Revision 13
2-21
3.3 V GTL+
35 mA
12
–
2.5 V GTL+
33 mA
15
–
HSTL (I)
8 mA
50
HSTL (II)
15 mA 4
25
SSTL2 (I)
15 mA
27
31
SSTL2 (II)
18 mA
13
15
SSTL3 (I)
14 mA
44
69
SSTL3 (II)
21 mA
18
32
Table 2-20 I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCI
R((WEAK PULL-UP)1
(
)
R(WEAK PULL-DOWN)2
(
)
Min.
Max.
Min.
Max.
3.3 V
10 k
45 k
10 k
45 k
3.3 V (Wide
Range I/Os)
10 k
45 k
10 k
45 k
2.5 V
11 k
55 k
12 k
74 k
1.8 V
18 k
70 k
17 k
110 k
1.5 V
19 k
90 k
19 k
140 k
Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)
Table 2-19 I/O Output Buffer Maximum Resistances1 (continued)
Standard
Drive Strength
RPULL-DOWN ()2
RPULL-UP ()3
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. Output drive strength is below JEDEC specification.