Revision 13 2-21 3.3 V GTL+ 35 mA 12 鈥� 2.5 V GTL+ 33 mA 15 鈥� HSTL (I) 8 mA 50 HSTL (II) 15 mA
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3PE600-1PQG208
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 92/162闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 600000 GATES 208-PQFP
妯欐簴鍖呰锛� 24
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 147
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�鐣跺墠绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�
ProASIC3E Flash Family FPGAs
Revision 13
2-21
3.3 V GTL+
35 mA
12
鈥�
2.5 V GTL+
33 mA
15
鈥�
HSTL (I)
8 mA
50
HSTL (II)
15 mA 4
25
SSTL2 (I)
15 mA
27
31
SSTL2 (II)
18 mA
13
15
SSTL3 (I)
14 mA
44
69
SSTL3 (II)
21 mA
18
32
Table 2-20 I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCI
R((WEAK PULL-UP)1
(
)
R(WEAK PULL-DOWN)2
(
)
Min.
Max.
Min.
Max.
3.3 V
10 k
45 k
10 k
45 k
3.3 V (Wide
Range I/Os)
10 k
45 k
10 k
45 k
2.5 V
11 k
55 k
12 k
74 k
1.8 V
18 k
70 k
17 k
110 k
1.5 V
19 k
90 k
19 k
140 k
Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax 鈥� VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)
Table 2-19 I/O Output Buffer Maximum Resistances1 (continued)
Standard
Drive Strength
RPULL-DOWN ()2
RPULL-UP ()3
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax 鈥� VOHspec) / IOHspec
4. Output drive strength is below JEDEC specification.
鐩搁棞PDF璩囨枡
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A3PE600-1PQ208 IC FPGA 600000 GATES 208-PQFP
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