Revision 13 2-67 Global Resource Characteristics A3PE600 Clock Tree Topology Clock delays are device-specific. Figure" />
參數(shù)資料
型號: A3PE600-1FGG484I
廠商: Microsemi SoC
文件頁數(shù): 143/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 484-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3E
RAM 位總計(jì): 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
ProASIC3E Flash Family FPGAs
Revision 13
2-67
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-38 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.
It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
page 2-68, and Table 2-97 on page 2-68 present minimum and maximum global clock delays within the
device. Minimum and maximum delays are measured with minimum and maximum loading.
Figure 2-38 Example of Global Tree Use in an A3PE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
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A3PE600-1PQ208 功能描述:IC FPGA 600000 GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA(17x17)