Revision 13 2-141 Table 2-217 RAM512X18 鈥� Applies to 1.2 V DC Core Voltage Commercial-Cas" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3P250L-FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 65/242闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 250K 144-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3L Low Power Flash FPGAs
Revision 13
2-141
Table 2-217 RAM512X18 鈥� Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
鈥�1
Std. Units
tAS
Address setup time
0.33 0.39
ns
tAH
Address hold time
0.00 0.00
ns
tENS
REN, WEN setup time
0.12 0.14
ns
tENH
REN, WEN hold time
0.08 0.09
ns
tDS
Input data (WD) setup time
0.24 0.29
ns
tDH
Input data (WD) hold time
0.00 0.00
ns
tCKQ1
Clock High to new data valid on RD (output retained, WMODE = 0)
2.88 3.39
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
1.19 1.40
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same
address 鈥� applicable to opening edge
0.25 0.29
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same
address 鈥� applicable to opening edge
0.31 0.36
ns
tRSTBQ
RESET Low to data out Low on RD (flow-through)
1.23 1.45
ns
RESET Low to data out Low on RD (pipelined)
1.23 1.45
ns
tREMRSTB
RESET removal
0.38 0.45
ns
tRECRSTB
RESET recovery
2.00 2.35
ns
tMPWRSTB RESET minimum pulse width
0.63 0.72
ns
tCYC
Clock cycle time
5.75 6.61
ns
FMAX
Maximum frequency
174 151 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values
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