2-12 Revision 13 Table 2-16 Summary of I/O Output Buffer Power (per pin) 鈥� Def" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P250L-FGG144I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 164/242闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 250K 144-FBGA
妯欐簴鍖呰锛� 160
绯诲垪锛� ProASIC3L
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.14V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 144-LBGA
渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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ProASIC3L DC and Switching Characteristics
2-12
Revision 13
Table 2-16 Summary of I/O Output Buffer Power (per pin) 鈥� Default I/O Software Settings 1
Applicable to Advanced I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
鈥�
141.97
2.5 V LVCMOS
5
2.5
鈥�
79.98
1.8 V LVCMOS
5
1.8
鈥�
52.26
1.5 V LVCMOS (JESD8-11)
5
1.5
鈥�
35.62
1.2 V LVCMOS
5
1.2
鈥�
21.29
3.3 V PCI
10
3.3
鈥�
201.02
3.3 V PCI-X
10
3.3
鈥�
201.02
Differential
LVDS
鈥�
2.5
7.74
89.71
LVPECL
鈥�
3.3
19.54
167.54
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
Table 2-17 Summary of I/O Output Buffer Power (per pin) 鈥� Default I/O Software Settings 1
Applicable to Standard Plus I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC7 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
鈥�
125.97
2.5 V LVCMOS
5
2.5
鈥�
70.82
1.8 V LVCMOS
5
1.8
鈥�
36.39
1.5 V LVCMOS (JESD8-11)
5
1.5
鈥�
25.34
1.2 V LVCMOS
5
1.2
鈥�
16.24
3.3 V PCI
10
3.3
鈥�
184.92
3.3 V PCI-X
10
3.3
鈥�
184.92
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
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