參數(shù)資料
型號: A29L160TG-90
廠商: AMIC Technology Corporation
英文描述: 2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
中文描述: 2米x 8位/ 1米× 16位CMOS 3.0伏只,引導(dǎo)扇區(qū)閃存
文件頁數(shù): 18/42頁
文件大小: 572K
代理商: A29L160TG-90
A29L160A Series
(May, 2005, Version 0.1)
17
AMIC Technology, Corp.
Table 9. A29L160A Command Definitions
Bus Cycles (Notes 2 - 5)
Third
Addr Data Addr
555
AAA
555
AAA
555
AAA
555
AAA
First
Second
Fourth
Fifth
Sixth
Addr
Command
Sequence
(Note 1)
C
Addr Data Addr Data
RA
RD
XXX
F0
555
AAA
555
AAA
555
AAA
555
AAA
Data
Addr Data
Data
Read (Note 6)
Reset (Note 7)
1
1
Word
Byte
Word
Byte
Word
Byte
Word
Byte
2AA
555
2AA
555
2AA
555
2AA
555
Manufacturer ID
4
AA
55
90
X00
37
X01
X02
X01 2249
X02
X03
X06
(SA)
X02
22C4
C4
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
4
AA
55
90
4
AA
55
90
49
Continuation ID
4
AA
55
90
7F
XX00
XX01
00
01
PD
Word
555
2AA
555
A
Sector Protect Verify
(Note 9)
Byte
4
AAA
AA
555
55
AAA
90
(SA)
X04
PA
Word
Byte
Byte
Byte
Word
Byte
55
AA
555
AAA
555
AAA
XXX A0
2AA
555
2AA
555
PA
55
A0
CFI Query (Note 10)
1
98
555
AAA
555
AAA
Program
4
AA
Unlock Bypass
3
AA
55
20
Unlock Bypass Program (Note
11)
Unlock Bypass Reset (Note 12)
2
PD
2
XXX 90
555
AAA
555
AAA
XXX
XXX
XXX
2AA
555
2AA
555
00
55
Word
Byte
Word
Byte
555
AAA
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
555
AAA
SA
Chip Erase
6
AA
80
AA
55
10
Sector Erase
6
AA
55
80
AA
55
30
Erase Suspend (Note 13)
Erase Resume (Note 14)
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
WE
or
CE
pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of
WE
or
CE
pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A19 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O
5
goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more
information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
14. The Erase Resume command is valid only during the Erase Suspend mode.
1
1
B0
30
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