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參數(shù)資料
| 型號： | A29DL324V |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 32 Megabit (4M x 8-Bit/2M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 32兆位（4米× 8-Bit/2M x 16位），3.0伏的CMOS只，同時作業(yè)快閃記憶體 |
| 文件頁數(shù)： | 27/50頁 |
| 文件大?。?/td> | 771K |
| 代理商： | A29DL324V |
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A29DL32x Series
PRELIMINARY (May, 2005, Version 0.0)
26
AMIC Technology, Corp.
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: I/O
2
, I/O
3
, I/O
5
, I/O
6
, and I/O
7
.
Table 13 and the following subsections describe the function
of these bits. I/O
7
and I/O
6
each offer a method for
determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/
BY
, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
I/O
7
:
Data
Polling
The
Data
Polling bit, I/O
7
, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend.
Data
Polling is
valid after the rising edge of the final
WE
pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device outputs
on I/O
7
the complement of the datum programmed to I/O
7
.
This I/O
7
status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O
7
.
The system must provide the program address to read valid
status information on I/O
7
. If a program address falls within a
protected sector,
Data
Polling on I/O
7
is active for
approximately 1
μ
s, then the device returns to reading array
data.
During the Embedded Erase algorithm,
Data
Polling
produces a "0" on I/O
7
. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data
Polling produces a "1" on I/O
7
. The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O
7
.
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Data
Polling on I/O
7
is
active for approximately 100
μ
s, then the bank returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O
7
at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, I/O
7
may change asynchronously with I/O
0
–
I/O
6
while Output Enable (
OE
) is asserted low. That is, the
device may change from providing status information to valid
data on I/O
7
. Depending on when the system samples the
I/O
7
output, it may read the status or valid data. Even if the
device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O
0
-I/O
6
may be still
invalid. Valid data on I/O
0
-I/O
7
will appear on successive read
cycles.
Table 13 shows the outputs for
Data
Polling on I/O
7
. Figure
5 shows the
Data
Polling algorithm. Figure 19 in the AC
Characteristics section shows the
Data
Polling timing
diagram.
START
Read I/O
7
-I/O
0
Address = VA
I/O
7
= Data
FAIL
No
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O
7
should be rechecked even if I/O
5
= "1" because
I/O
7
may change simultaneously with I/O
5
.
No
Read I/O
7
- I/O
0
Address = VA
I/O
5
= 1
I/O
7
= Data
Yes
No
PASS
Yes
Yes
Figure 5. Data Polling Algorithm
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