參數(shù)資料
型號(hào)： A1415A-1VQG100I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 8/90頁(yè)
文件大小： 0K
描述： IC FPGA 1500 GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 200
輸入/輸出數(shù)： 80
門數(shù)： 1500
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Detailed Specifications
2- 8
R e v ision 3
Module Output Connections
Module outputs have dedicated output segments. Output segments extend vertically two channels above
and two channels below, except at the top or bottom of the array. Output segments twist, as shown in
Figure 10, so that only four vertical tracks are required.
LVT Connections
Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module
pair in the array shares four LVTs that span the length of the column. Any module in the column pair can
connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses
connected directly to the driver stage of the module output, bypassing the isolation transistor. FF
antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower
resistance value.
Antifuse Connections
In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed
antifuse (XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a
few of the C-module and S-module inputs can be connected to the clock networks. To further reduce
loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock
inputs of the S-module.
Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and programming circuits controlled by the
temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family
devices. The ACT 3 family also includes support for two Actionprobe circuits, allowing complete
observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1415A-1VQG100M 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 150MHZ 0.8UM 5V 100VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 1500 GATES 100-VQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 80 I/O 100VQFP
A1415A-2PL84C 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 84PLCC - Rail/Tube
A1415A-2PL84I 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 84PLCC - Rail/Tube
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A1415A-2PLG84I 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 200MHZ 0.8UM 5V 84PLCC - Rail/Tube
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