參數(shù)資料
型號(hào): A1242LUA-I2-T
廠商: Allegro Microsystems Inc
文件頁數(shù): 12/12頁
文件大?。?/td> 297K
描述: IC LATCH HALL EFFECT 3-SIP
產(chǎn)品培訓(xùn)模塊: Current Sensor
標(biāo)準(zhǔn)包裝: 500
傳感范圍: 80G 跳閘,-80G 釋放
類型: 單極開關(guān)
電源電壓: 3.5 V ~ 24 V
電流 - 電源: 6.9mA
輸出類型: 數(shù)字式,開漏極
特點(diǎn): 穩(wěn)壓電壓
工作溫度: -40°C ~ 150°C
封裝/外殼: 3-SIP
供應(yīng)商設(shè)備封裝: 3-SIP
包裝: 散裝
Two-Wire Chopper-Stabilized Hall Effect Latch
A1242
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package UA, 3-Pin SIP
2   3
1
0.79 REF
1.27 NOM
2.16
MAX
0.51
REF
45?/DIV>
C
45?/DIV>
B
E
E
E
2.04
1.44
Gate burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
D
Branding scale and appearance at supplier discretion
Hall element, not to scale
Active Area Depth, 0.50 mm REF
For Reference Only; not for tooling use (reference DWG-9049)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Standard Branding Reference View
   = Supplier emblem
  N = Last two digits of device part number
  T = Temperature code
NNT
1
Mold Ejector
Pin Indent
Branded
Face
4.09
+0.08
0.05
0.41
+0.03
0.06
3.02
+0.08
0.05
0.43
+0.05
0.07
15.75 ?.51
1.52 ?.05
Copyright ?005-2010, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegros products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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