A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s (continued) (Wor s t - C as e M i l" />
鍙冩暩璩囨枡
鍨嬭櫉锛� A1020B-1PLG68C
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩锛� 46/98闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 2K GATES 68-PLCC COM
妯欐簴鍖呰锛� 19
绯诲垪锛� ACT™ 1
LAB/CLB鏁革細 547
杓稿叆/杓稿嚭鏁革細 57
闁€鏁革細 2000
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 68-LCC锛圝 褰㈠紩绶氾級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 68-PLCC锛�24.23x24.23锛�
50
A3 21 00 DX Ti m i n g Ch ar ac te r i st i c s (continued)
(Wor s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad to Y
1.9
2.6
ns
tINGO
Input Latch Gate-to-Output
4.0
5.3
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Setup
0.7
0.9
ns
tILA
Latch Active Pulse Width
6.1
8.1
ns
Input Module Predicted Routing Delays1
tIRD1
FO=1 Routing Delay
2.2
2.9
ns
tIRD2
FO=2 Routing Delay
2.8
3.8
ns
tIRD3
FO=3 Routing Delay
3.5
4.7
ns
tIRD4
FO=4 Routing Delay
3.5
4.7
ns
tIRD8
FO=8 Routing Delay
5.6
7.5
ns
Global Clock Network
tCKH
Input Low to High
FO=32
FO=635
6.5
7.9
8.7
10.6
ns
tCKL
Input High to Low
FO=32
FO=635
6.6
8.8
11.8
ns
tPWH
Minimum Pulse Width High
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
tPWL
Minimum Pulse Width Low
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
tCKSW
Maximum Skew
FO=32
FO=635
1.8
2.4
ns
tSUEXT
Input Latch External Setup
FO=32
FO=635
0.0
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
tP
Minimum Period (1/fmax)
FO=32
FO=635
7.1
7.9
9.5
10.5
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
140
126
105
95
MHz
Note:
1.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
鐩搁棞PDF璩囨枡
PDF鎻忚堪
749193-2 CONN 50POS AMPLMT BACKSHL STYL A
ASC44DRES-S93 CONN EDGECARD 88POS .100 EYELET
A42MX16-1PQG208 IC FPGA MX SGL CHIP 24K 208-PQFP
A42MX16-1PQ208 IC FPGA MX SGL CHIP 24K 208-PQFP
M1AFS250-1PQG208I IC FPGA 2MB FLASH 250K 208-PQFP
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鍙冩暩鎻忚堪
A1020B-1PLG68I 鍔熻兘鎻忚堪:IC FPGA 2K GATES 68-PLCC IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�:6036 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:360 闁€鏁�:108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1020B-1PLG84C 鍔熻兘鎻忚堪:IC FPGA 2K GATES 84-PLCC COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�:6036 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:360 闁€鏁�:108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1020B-1PLG84I 鍔熻兘鎻忚堪:IC FPGA 2K GATES 84-PLCC IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�:6036 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:360 闁€鏁�:108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1020B-1PLG84M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA ACT 1 Family 2K Gates 547 Cells 57MHz 1.0um Technology 5V 84-Pin PLCC 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 2K GATES 84-PLCC MIL
A1020B-1PQ100C 鍔熻兘鎻忚堪:IC FPGA 2K GATES 100-PQFP COM RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�:6036 閭忚集鍏冧欢/鍠厓鏁�:- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�:360 闁€鏁�:108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
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娣诲姞鏇村閲囪臣

鎴戠殑鑱郴鏂瑰紡

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