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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-VQG80C
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 16/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1200 GATES 80-VQFP COM
妯欐簴鍖呰锛� 90
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 80-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 80-VQFP锛�14x14锛�
23
Hi R e l F P GA s
Du al - P or t S RAM T i mi ng Wa ve f o r m s
3200 DX S R A M W ri te Ope rat i o n
Note:
Identical timing for falling-edge clock.
3200 DX S R A M S y nch ro nous R ead Oper at i o n
Note:
Identical timing for falling-edge clock.
WCLK
WD[7:0]
WRAD[5:0]
WEN
BLKEN
Valid
tRCKHL
tWENSU
tBENSU
tWENH
tBENH
tADSU
tADH
RCLK
REN
RDAD[5:0]
RD[7:0]
Old Data
Valid
tRCKHL
tCKHL
tRENH
tRCO
tADH
tDOH
tADSU
New Data
tRENSU
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1AGL1000V5-FGG484 IC FPGA 1KB FLASH 1M 484-FBGA
M1AGL1000V5-FG484 IC FPGA 1KB FLASH 1M 484-FBGA
AGL1000V5-FG484 IC FPGA 1KB FLASH 1M 484FBGA
AFS600-FGG484 IC FPGA 4MB FLASH 600K 484FBGA
M1AFS600-FG484 IC FPGA 4MB FLASH 600K 484-FBGA
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A1010B-VQG80I 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010J1AQE2 鍒堕€犲晢:Switchcraft 鍔熻兘鎻忚堪:TOGGLE SWITCH
A1010-JQ44B 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA)
A1010-JQ44C 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA)
A1010-JQ44I 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:Field Programmable Gate Array (FPGA)
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京銆�

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娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

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