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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A1010B-VQ80I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 13/98闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1200 GATES 80-VQFP IND
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 80-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-VQFP锛�14x14锛�
20
S equ en ti a l Ti m i ng Cha r a c t e ri s t i c s (continued)
Fl i p - F l ops and La tc h e s (120 0XL /3 200D X, AC T 2, a nd A C T 1)
Note:
1.
D represents all data functions involving A, B, and S for multiplexed flip-flops.
(Positive edge triggered)
D
E
CLK
CLR
PRE
Y
D1
G, CLK
E
Q
PRE, CLR
tWCLKA
tWASYN
tHD
tSUENA
tSUD
tRS
tA
tCO
tHENA
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A1010B-VQG80I IC FPGA 1200 GATES 80-VQFP IND
971-025-030R121 BACKSHELL DB25 DIECAST NKL 45DEG
A42MX16-2PQG100I IC FPGA MX SGL CHIP 24K 100-PQFP
CAT24C05YI-GT3 IC EEPROM 4KBIT 400KHZ 8TSSOP
A42MX16-2PQ100I IC FPGA MX SGL CHIP 24K 100-PQFP
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