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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A1010B-VQ80C |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 27/98闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 1200 GATES 80-VQFP COM |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ACT™ 1 |
| LAB/CLB鏁�(sh霉)锛� | 295 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 闁€鏁�(sh霉)锛� | 1200 |
| 闆绘簮闆诲锛� | 4.5 V ~ 5.5 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 80-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 80-VQFP锛�14x14锛� |
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33
Hi R e l F P GA s
A1 28 0XL Ti m i ng Cha r act e r i s t i cs
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
3.7
4.3
ns
tCO
Sequential Clk to Q
3.7
4.3
ns
tGO
Latch G to Q
3.7
4.3
ns
tRS
Flip-Flop (Latch) Reset to Q
3.7
4.3
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.7
2.1
ns
tRD2
FO=2 Routing Delay
2.5
3.0
ns
tRD3
FO=3 Routing Delay
3.1
3.6
ns
tRD4
FO=4 Routing Delay
3.7
4.3
ns
tRD8
FO=8 Routing Delay
7.0
8.3
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.1
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
5.3
6.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
5.3
6.1
ns
tA
Flip-Flop Clock Input Period
10.7
12.3
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
90
75
MHz
Notes:
1.
For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4.
Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A1010B-VQG80C | IC FPGA 1200 GATES 80-VQFP COM |
| M1AGL1000V5-FGG484 | IC FPGA 1KB FLASH 1M 484-FBGA |
| M1AGL1000V5-FG484 | IC FPGA 1KB FLASH 1M 484-FBGA |
| AGL1000V5-FG484 | IC FPGA 1KB FLASH 1M 484FBGA |
| AFS600-FGG484 | IC FPGA 4MB FLASH 600K 484FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A1010BVQ80I | 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:1010BVQ80I |
| A1010B-VQ80I | 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A1010B-VQG80C | 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A1010B-VQG80I | 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛� |
| A1010J1AQE2 | 鍒堕€犲晢:Switchcraft 鍔熻兘鎻忚堪:TOGGLE SWITCH |
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