Note: 1. D repres" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-PQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 11/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1200 GATES 100-PQFP IND
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 66
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-BQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-PQFP锛�14x20锛�
19
Hi R e l F P GA s
S equ en ti a l Ti m i ng Cha r a c t e ri s t i c s
Fl i p - F l ops and La tc h e s (AC T 3)
Note:
1.
D represents all data functions involving A, B, and S for multiplexed flip-flops.
(Positive edge triggered)
D
E
CLK
CLR
Y
D1
G, CLK
E
Q
CLR
tWCLKA
tWASYN
tHD
tSUENA
tSUD
tCLR
tA
tCO
tHENA
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A1010B-PQG100I IC FPGA 1200 GATES 100-PQFP IND
A42MX09-3VQ100 IC FPGA MX SGL CHIP 14K 100VQFP
A42MX09-3VQG100 IC FPGA MX SGL CHIP 14K 100VQFP
A3P600L-FG484I IC FPGA 1KB FLASH 600K 484-FBGA
A3P600L-FGG484I IC FPGA 1KB FLASH 600K 484-FBGA
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A1010B-PQG100C 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 100-PQFP COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
A1010B-PQG100I 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 100-PQFP IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:ACT™ 1 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010BSTDCQ84B 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:ASIC
A1010BSTDCQ84C 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:ASIC
A1010BSTDCQ84E 鍒堕€犲晢:鏈煡寤犲 鍒堕€犲晢鍏ㄧū:鏈煡寤犲 鍔熻兘鎻忚堪:ASIC