(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-1PLG44C
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 39/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1200 GATES 44-PLCC COM
妯欐簴鍖呰锛� 27
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 44-LCC锛圝 褰㈠紩绶氾級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 44-PLCC锛�16.59x16.59锛�
44
A1 41 00 A Ti m i ng Cha r act e r i s t i cs
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
3.0
3.5
ns
tCO
Sequential Clock to Q
3.0
3.5
ns
tCLR
Asynchronous Clear to Q
3.0
3.5
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
1.9
2.1
ns
tRD3
FO=3 Routing Delay
2.1
2.5
ns
tRD4
FO=4 Routing Delay
2.6
2.9
ns
tRD8
FO=8 Routing Delay
4.2
4.9
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
1.0
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.6
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.6
ns
tWASYN
Asynchronous Pulse Width
4.8
5.6
ns
tWCLKA
Flip-Flop Clock Pulse Width
4.8
5.6
ns
tA
Flip-Flop Clock Input Period
9.9
11.6
ns
fMAX
Flip-Flop Clock Frequency
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
4.9
ns
tICKY
Input Reg IOCLK Pad to Y
7.0
8.2
ns
tOCKY
Output Reg IOCLK Pad to Y
7.0
8.2
ns
tICLRY
Input Asynchronous Clear to Y
7.0
8.2
ns
tOCLRY
Output Asynchronous Clear to Y
7.0
8.2
ns
Input Module Predicted Routing Delays2, 3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1.
For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3.
Optimization techniques may further reduce delays by 0 to 4 ns.
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